Enable timer preload function to prevent output glitches #224
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Enable shadow registers for timer compare values to ensure updates only takes effect at timer overflow, preventing mid-cycle glitches in PWM and other output compare modes.
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Problem
analogWrite()on CH32V003 produces occasional glitches when updating the PWM duty cycle. Changes take effect mid-cycle, rather than at cycle boundaries.Solution
Enable timer preload registers (shadow registers) for PWM channels to synchronize compare value updates with timer overflow events.
Changes
TIM_OCPreload_Enablefor timer channels in PWM modeanalogWrite()callsFixes: #223