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    • iEDA

      Public
      An open-source EDA infrastructure and tools from netlist to GDS
      C++
      59481101Updated Jan 10, 2026Jan 10, 2026
    • iPCL-R

      Public
      A pre-training foundation model for chip layout routing
      Python
      2500Updated Jan 8, 2026Jan 8, 2026
    • AiEDA

      Public
      RTL-to-Vector-to-GDS
      Python
      136000Updated Dec 5, 2025Dec 5, 2025
    • AI4EDA: AI Works for Electronic Design Automation
      2900Updated Dec 3, 2025Dec 3, 2025
    • 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
      Verilog
      19000Updated Nov 13, 2025Nov 13, 2025
    • ieda-website-resources

      Public
      :computer: The resource repository for the website of iEDA project.
      2000Updated Sep 1, 2025Sep 1, 2025
    • :computer: The official website of iEDA project.
      Vue
      22100Updated Sep 1, 2025Sep 1, 2025
    • YSYX Chips
      Verilog
      0200Updated Aug 12, 2025Aug 12, 2025
    • iMCP

      Public
      The iMCP is a mcp server for opensource EDA Tool iEDA.
      Python
      1100Updated Aug 1, 2025Aug 1, 2025
    • iChipAgent

      Public
      AI agent for chip design
      TypeScript
      2500Updated Aug 1, 2025Aug 1, 2025
    • AI for EDA tasks and models
      Python
      2300Updated Jul 26, 2025Jul 26, 2025
    • iDATA

      Public
      AI for EDA dataset
      2200Updated Jul 10, 2025Jul 10, 2025
    • Delay-Driven Rectilinear Steiner Tree Construction
      C++
      1100Updated Apr 30, 2025Apr 30, 2025
    • iATPG

      Public
      Automatic Test Pattern Generation Tool
      Max
      0200Updated Mar 3, 2025Mar 3, 2025
    • iFlow

      Public
      A chip design flow with open-source EDA tools, PDKs
      Verilog
      0300Updated Oct 26, 2024Oct 26, 2024
    • Logic Synthesis Platform.
      C++
      1300Updated Oct 22, 2024Oct 22, 2024
    • iTraining

      Public
      iEDA water-drop training initiative
      C++
      11301Updated Sep 10, 2024Sep 10, 2024
    • iEDA-web-discussion
      0000Updated Aug 8, 2024Aug 8, 2024
    • EDA standard file format parsers: Verilog, Liberty, SPEF, VCD, SDF, SDC,
      C++
      2900Updated Nov 23, 2023Nov 23, 2023
    • iMap

      Public
      Logic optimization and technology mapping tool.
      C++
      52000Updated Oct 12, 2023Oct 12, 2023