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    • Nios V Processor example designs targeting Altera Agilex 7 Development Kits
      SystemVerilog
      Other
      0000Updated Mar 20, 2026Mar 20, 2026
    • Hardware and software collateral for altera-fpga developer website
      HTML
      1400Updated Mar 17, 2026Mar 17, 2026
    • settings

      Public
      Contains configuration files and scripts for the altera-fpga Github site
      2009Updated Mar 15, 2026Mar 15, 2026
    • Linux development repository for socfpga
      C
      Other
      312283015Updated Mar 13, 2026Mar 13, 2026
    • Altera Agilex 7 PTP System Example Design
      SystemVerilog
      0000Updated Mar 9, 2026Mar 9, 2026
    • C
      0300Updated Mar 1, 2026Mar 1, 2026
    • Official Intel SOCFPGA Arm-TF repository. Note: (1) A "RC" labeled branch is for internal active development use and customer early access without official cust…
      C
      Other
      161806Updated Feb 28, 2026Feb 28, 2026
    • This is a software reference code to implement the FPGA remote debug feature. User will compile the reference code into a user space application which exchanged…
      C
      BSD 3-Clause "New" or "Revised" License
      81521Updated Feb 28, 2026Feb 28, 2026
    • Altera Agilex 5 HPS-to-FPGA Interface Demos
      Tcl
      MIT No Attribution
      3710Updated Feb 23, 2026Feb 23, 2026
    • 4Kp60 Multi-Sensor HDR Camera Solution System Example Design for Agilex™ 3 Devices
      Tcl
      Other
      0000Updated Feb 18, 2026Feb 18, 2026
    • Nios V Processor example designs targeting Altera Agilex 3 Development Kit
      Tcl
      Other
      0000Updated Feb 18, 2026Feb 18, 2026
    • Nios V Processor example designs targeting Altera Agilex 5 Development Kits
      C++
      Other
      1400Updated Feb 18, 2026Feb 18, 2026
    • Official Intel SOCFPGA U-Boot repository. Note: (1) A "RC" labeled branch is for internal active development use and customer early access without official cust…
      C
      Other
      154119010Updated Feb 11, 2026Feb 11, 2026
    • Altera Agilex 5 Ethernet System Example Design
      SystemVerilog
      Other
      0000Updated Feb 3, 2026Feb 3, 2026
    • Agilex 5 PTP System Example Design
      SystemVerilog
      Other
      0000Updated Jan 30, 2026Jan 30, 2026
    • Altera FPGA Real-Time Meta Layer
      BitBake
      Other
      0000Updated Jan 28, 2026Jan 28, 2026
    • NVIDIA Holoscan Sensor Bridge - Bring Your Own Sensor (BYOS) over Ethernet
      C++
      Apache License 2.0
      21000Updated Jan 16, 2026Jan 16, 2026
    • Shell
      MIT License
      51620Updated Jan 15, 2026Jan 15, 2026
    • Altera Agilex 5 E-Series GSRD
      Tcl
      Other
      4400Updated Jan 12, 2026Jan 12, 2026
    • Altera Modular Design Toolkit
      Tcl
      Other
      0400Updated Jan 9, 2026Jan 9, 2026
    • Altera Arria 10 GSRD
      Tcl
      Other
      0100Updated Jan 9, 2026Jan 9, 2026
    • Altera Stratix 10 GSRD
      Tcl
      Other
      0000Updated Jan 9, 2026Jan 9, 2026
    • Altera Agilex 7 F-Series GSRD
      Tcl
      Other
      0000Updated Jan 9, 2026Jan 9, 2026
    • Altera Agilex 3 C-series GSRD
      Makefile
      Other
      0000Updated Jan 9, 2026Jan 9, 2026
    • Meta Altera FPGA Yocto Layer
      BitBake
      0001Updated Jan 9, 2026Jan 9, 2026
    • libfcs

      Public
      Altera FPGA Crypto Services Library
      C
      MIT No Attribution
      2001Updated Jan 9, 2026Jan 9, 2026
    • This repository contains Yocto Project application and customization meta layer for GSRD(Golden Software Reference Design)
      BitBake
      MIT License
      131632Updated Jan 9, 2026Jan 9, 2026
    • Agilex Holoscan Sensor Bridge System Example Designs
      Tcl
      Other
      0000Updated Dec 15, 2025Dec 15, 2025
    • Agilex 4Kp30 Multi-Sensor Camera with AI Inference Solution System Example Design
      C++
      Other
      0100Updated Dec 5, 2025Dec 5, 2025
    • Agilex 5 E-Series HPS Enhanced System Example Design which includes memory and Ethernet interface
      SystemVerilog
      Other
      2200Updated Dec 4, 2025Dec 4, 2025