An external reset, generated by a button, a simple circuit with a loading capacity and a Schmitt trigger, or a watchdog, is asynchronous to the synchronous design. Therefore, like any other asynchronous inputs, it needs to be synchronized. The usual circuit for this is 2 flip-flops. Nothing more. Reset itself is not used in this synchronizer.
Failing to proper synchronize reset might lead to parts of your circuit being reset in different clock cycles. I have seen an example in a real industrial code that uses a one hot encoded state machine coming out after reset in an invalid state some times. Some flops received reset one cycle later than others. Finding out this issue (without seeing the code) actually resulted in a very lucrative consulting job: doing some code review without any responsibility for EUR 4000 :-)
So in plain Chisel the correct way to do it in my opinion is: reset = NextReg(NextReg(resetIn))
No usage of reset on those two flip-flops. @Anas, where did you get your inspiration of your circuit that you coded in Verilog?
Synchronizing reset is independent from how your circuit uses reset: asynchronous or synchronous. This is a style difference depending on company culture, maybe some way is cheaper (I don't know and should check the SykWater130 PDK), or just historical. Again: even if you use asynchronous flip-flops in your design, the reset has to be properly synchronized to the design's clock.
Have some slides on Caravel and the flow. Reading: https://info.efabless.com/knowledge-base/development-milestones-and-checklist-for-digital-design-projects-with-chipignite
animation of GDS: https://znah.net/tt09/
- what is synthesis
- basic elements
- standard cells
- show a standard cell in a layout