This repository contains the material for the 13-week course 02118 - Introduction to Chip Design at the Technical University of Denmark (DTU). This course was developed with support from the Edu4Chip project.
- Practicalities
- Course Aim
- Reading Material
- Lecture Plan
- Project
- Exam
- Learning Objectives
- License
- Funding
The course runs on Wednesdays from 13:00 to 17:00 in Building 308 - Room 017.
Each weekly session consist of a lecture and laboratory work. Some session will be fully dedicated to laboratory work (especially at the end of the course when you are expected to work on your project).
The course has two teachers:
Guest Lectures:
- Luca Pezzarossa
- Ole Richter
- Kasper Hesse
Install the LibreLane tools locally or use the server chipdesign1.compute.dtu.dk. The tools are currently usable on Linux and MacOS (even native with Mac Silicon). For Windows use WSL2 to have a Linux environment. There is no official support for Windows available. See Section 1.2 in the Chip Design Booklet for installation instructions.
This course is an introduction to the design of digital integrated circuits. It covers the basics of digital circuits, the tools used, and the process of designing a chip. The course is based open-source tools and open-source PDKs. The course also gives the possibility for student projects to be taped out on Tiny Tapeout.
- Lecture slides and lab material
- The textbook CMOS VLSI Design, A Circuits and Systems Perspective by Neil H. E. Weste and David Harris, also available as PDF
- The Chip Design Booklet is a start of notes and exercises for the course.
- The material related to the open-source tools we use, including installation instructions: LibreLane Documentation
- For a quick start you can explore LibreLane in the browser
- Caravel Documentation
- Chisel Book (as reference when doing designs in Chisel)
- Overview of chip design and its importance in modern electronics
- Basic terminology and concepts
- Introduction to the LibreLane ASIC design flow
- AISC with standard cells
- PDK
- Local installation of the open-srouce tools (LibreLane)
- Running a "Hello World" example from Verilog source to GDSII
- Explore timing and size
- Explore different reset strategies
- See Section 1.3 in the Chip Design Booklet
- Lecture slides (also available as PDF in DTU-Learn)
- Weste and Harris: 1.1 and 1.12
- OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain
- Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper
- Tiny Tapeout: A Shared Silicon Tapeout Platform Accessible To Everyone
- The need for a controlled switch
- A brief history of the transistor
- The MOSFET transistor
- The NMOS inverter
- The CMOS inverter
- Other gates
- SiliWiz exercises
- See Lab 2 for instructions
- Lecture slides (also available as PDF in DTU-Learn)
- From the textbook:
- 1.3
- 1.4.1, 1.4.2, 1.4.3, 1.4.4, 1.4.5
- 1.5.1, 1.5.2
- 2.1, 2.2*, 2.3*
- quick read, no need to go into details with formulas
- Introduction to standard cells
- Role of standard cells in digital design
- Components of a standard cell library
- Types of standard cells (e.g., logic gates, flip-flops)
- Power, performance, and area
- Characterization of standard cells
- Models and simulation
- Simulate a SkyWater130 standard cell in Spice
- Discussion about the project
- Form and register groups in DTU Learn
- Choose a project component to work on (CPU, memory, peripherals, testing, etc.)
- Sign up in the GitHub repository
- See The Tapeout Project for instructions
- Details of the LibreLane ASIC design flow
- Individual tools and their outputs
- Caravel
- Tapeout options (CF, waver.space for production, IHP)
- Wishbone bus overview
- Project discusion
- Run steps of the LibreLane flow on a simple design from Python
- According to Section 1.4 in the Chip Design Booklet
- Explore the outputs of the individual stages
- Harden our Caravel framework with a simple peripheral
- Write a simple Wishbone peripheral (in Chisel)
- See Section 2.3.9 in the Chip Design Booklet
- Lecture slides (also available as PDF in DTU-Learn)
- Article on OpenLane2
- LibreLane Documentation
- Wishbone Specification
- Introduction to Verilog
- Comparison with Chisel
- See Lab Verilog for instructions
- Lecture slides (also available as PDF in DTU-Learn)
- Find good Verilog projects and read the code
- E.g., YARVI
- Introduction to verification
- Verification methodologies
- Simulation-based verification
- Testbench design
- Assertions and coverage metrics
- Brief overview of formal verification
- Industry Standards, tools, and frameworks in verification
The lab consists of two parts:
- One part introduces the testing setup in Caravel, see Caravel Testing Lab for instructions
- The other part works with formal verification methods. See Verification Lab for instructions
- Lecture slides (also available as PDF in DTU-Learn)
- Chip design rules
- Power distribution design, optimization, and analysis
- Digital design timing
- Clock distribution challenges and clock trees
- Timing closure
- Physical Verification
- Finish the Wishbone peripheral and test it in Caravel
- Get one Wildcat running in Caravel (blinking an LED)
- Start your project
- See The Tapeout Project and Project Start for background info
- Lecture slides (also available as PDF in DTU-Learn)
- Floorplanning
- Macros
- Placement
- W & H 1.10 Physical Design
- Using Macros in LibreLane
-
Memory types: FF, latches, SRAM
-
Memory organization
-
Memory macros (IP blocks)
-
Memory options with the SkyWater130 PDK
- Lecture slides (also available as PDF in DTU-Learn)
- From the textbook:
- 12.1
- 12.2, 12.2.1, 12.2.1.1, 12.2.1.2, 12.2.1.4
- OpenRam article
- Chip design at Demant
- Industrial design and implementation flow overview
- Design and implementation considerations for low power
- Challenges in lower design nodes (and/or at lower voltages)
- Finalise the functional implementation of your project
- not yet availble
- Work on project
- None
- not yet availble
- Work on project
- None
Finalize the project for tapeout.
- Run Timing closure and LVS
- Fix timing violations and handle design missmatches
- "tape out" your project
Each group presents their finalized project and discusses the results.
All original content in this repository, including text, code, and other materials, is licensed under the CC0 1.0 Universal license (see LICENSE file), unless otherwise noted.
Certain images in this repository are not covered by the CC0 license. These images may be subject to more restrictive copyright terms. Where applicable, copyright and licensing information is provided for these images in the relevant directories, file descriptions, or as text integrated in the images.
Funded by the European Union within the Edu4Chip - Joint Education for Advanced Chip Design in Europe project. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or European Health and Digital Executive Agency (HaDEA). Neither the European Union nor the granting authority can be held responsible for them.
