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build(deps): bump OpenFPGA from 7fff106 to c39c0b3 #880

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build(deps): bump OpenFPGA from 7fff106 to c39c0b3 #880

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2 changes: 1 addition & 1 deletion OpenFPGA
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Submodule OpenFPGA updated 78 files
+1 −1 VERSION.md
+6 −1 docs/source/manual/arch_lang/circuit_library.rst
+31 −1 docs/source/manual/arch_lang/circuit_model_examples.rst
+ − docs/source/manual/arch_lang/figures/stdcellmux.png
+59 −0 docs/source/manual/file_formats/clock_network.rst
+ − docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png
+4 −0 docs/source/manual/file_formats/index.rst
+80 −0 docs/source/manual/file_formats/reference_file.rst
+50 −0 docs/source/manual/file_formats/unique_blocks.rst
+67 −0 docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
+57 −0 libs/libarchopenfpga/src/check_circuit_library.cpp
+59 −0 libs/libarchopenfpga/src/circuit_library.cpp
+10 −0 libs/libarchopenfpga/src/circuit_library.h
+19 −0 libs/libarchopenfpga/src/read_xml_circuit_library.cpp
+9 −0 libs/libarchopenfpga/src/write_xml_circuit_library.cpp
+5 −0 libs/libclkarchopenfpga/arch/example_internal_drivers.xml
+97 −0 libs/libclkarchopenfpga/src/base/clock_network.cpp
+28 −0 libs/libclkarchopenfpga/src/base/clock_network.h
+9 −0 libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h
+68 −1 libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
+39 −0 libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
+64 −0 openfpga/src/annotation/append_clock_rr_graph.cpp
+209 −14 openfpga/src/annotation/device_rr_gsb.cpp
+52 −11 openfpga/src/annotation/device_rr_gsb.h
+157 −0 openfpga/src/annotation/read_xml_unique_blocks.cpp
+39 −0 openfpga/src/annotation/read_xml_unique_blocks.h
+89 −0 openfpga/src/annotation/route_clock_rr_graph.cpp
+190 −0 openfpga/src/annotation/write_xml_unique_blocks.cpp
+37 −0 openfpga/src/annotation/write_xml_unique_blocks.h
+99 −10 openfpga/src/base/openfpga_build_fabric_template.h
+17 −11 openfpga/src/base/openfpga_pb_pin_fixup.cpp
+1 −1 openfpga/src/base/openfpga_pb_pin_fixup.h
+2 −0 openfpga/src/base/openfpga_pb_pin_fixup_template.h
+155 −1 openfpga/src/base/openfpga_setup_command_template.h
+102 −13 openfpga/src/fabric/build_mux_modules.cpp
+123 −0 openfpga/src/utils/report_reference.cpp
+30 −0 openfpga/src/utils/report_reference.h
+1 −0 openfpga_flow/openfpga_arch/README.md
+236 −0 openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_laststage_mux_40nm_openfpga.xml
+49 −0 openfpga_flow/openfpga_cell_library/verilog/mux2.v
+1 −1 openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga
+52 −0 openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga
+79 −0 openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga
+82 −0 openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga
+37 −0 openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga
+49 −0 openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga
+80 −0 openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga
+14 −0 openfpga_flow/regression_test_scripts/basic_reg_test.sh
+1 −0 openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
+37 −0 ...k_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml
+35 −0 ...k_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml
+9 −0 ...basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml
+8 −0 ...basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml
+4 −0 ...s/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml
+57 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf
+12 −0 .../basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml
+12 −0 .../basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml
+1 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf
+34 −0 ..._tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml
+8 −0 .../basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml
+8 −0 .../basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml
+8 −0 ...ests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml
+4 −0 ...sic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml
+57 −0 ...pga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf
+35 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/config/task.conf
+22 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml
+42 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf
+1 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml
+92 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml
+42 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf
+1 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml
+92 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml
+35 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/config/task.conf
+41 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf
+1 −0 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml
+36 −0 openfpga_flow/tasks/basic_tests/report_reference/config/task.conf
+37 −0 openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2_last_stage/config/task.conf
+1 −1 yosys