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Merged
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Oct 17, 2024
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finish pb_fixup and readoptions merge #895

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5 changes: 5 additions & 0 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -130,6 +130,11 @@ FILE(COPY ${EBLIF_TRANSFORM_SRC_H}
DESTINATION
${EBLIF_TRANSFORM_DEST})

message(STATUS "NOTE: PATCHING VPR pack/pb_pin_fixup\n")
FILE(COPY ${PACKER_SRC_DIR}/post_routing_pb_pin_fixup.cpp
DESTINATION
${VPR_DEST_DIR}/src/pack)

# patch VPR
#FILE(COPY ${PACKER_SRC_DIR}/cluster.cpp
# ${PACKER_SRC_DIR}/cluster_util.cpp
Expand Down
46 changes: 42 additions & 4 deletions include/base_fix/PATCHED/read_options.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -101,6 +101,14 @@ struct ParseCircuitFormat {
conv_value.set_value(e_circuit_format::BLIF);
else if (str == "eblif")
conv_value.set_value(e_circuit_format::EBLIF);
else if (str == "verilog")
conv_value.set_value(e_circuit_format::VERILOG);
else if (str == "edif")
conv_value.set_value(e_circuit_format::EDIF);
else if (str == "edf")
conv_value.set_value(e_circuit_format::EDIF);
else if (str == "edn")
conv_value.set_value(e_circuit_format::EDIF);
else if (str == "fpga-interchange")
conv_value.set_value(e_circuit_format::FPGA_INTERCHANGE);
else {
Expand All @@ -120,6 +128,10 @@ struct ParseCircuitFormat {
conv_value.set_value("blif");
else if (val == e_circuit_format::EBLIF)
conv_value.set_value("eblif");
else if (val == e_circuit_format::VERILOG)
conv_value.set_value("verilog");
else if (val == e_circuit_format::EDIF)
conv_value.set_value("edif");
else {
VTR_ASSERT(val == e_circuit_format::FPGA_INTERCHANGE);
conv_value.set_value("fpga-interchange");
Expand All @@ -129,7 +141,7 @@ struct ParseCircuitFormat {
}

std::vector<std::string> default_choices() {
return {"auto", "blif", "eblif", "fpga-interchange"};
return {"auto", "blif", "eblif", "verilog", "edif", "edn", "edf", "fpga-interchange"};
}
};
struct ParseRoutePredictor {
Expand Down Expand Up @@ -398,6 +410,8 @@ struct ParsePlaceAlgorithm {
conv_value.set_value(CRITICALITY_TIMING_PLACE);
} else if (str == "slack_timing") {
conv_value.set_value(SLACK_TIMING_PLACE);
} else if (str == "congestion_aware") {
conv_value.set_value(CONGESTION_AWARE_PLACE);
} else {
std::stringstream msg;
msg << "Invalid conversion from '" << str << "' to e_place_algorithm (expected one of: " << argparse::join(default_choices(), ", ") << ")";
Expand All @@ -419,6 +433,8 @@ struct ParsePlaceAlgorithm {
conv_value.set_value("bounding_box");
} else if (val == CRITICALITY_TIMING_PLACE) {
conv_value.set_value("criticality_timing");
} else if (val == CONGESTION_AWARE_PLACE) {
conv_value.set_value("congestion_aware");
} else {
VTR_ASSERT(val == SLACK_TIMING_PLACE);
conv_value.set_value("slack_timing");
Expand All @@ -427,7 +443,7 @@ struct ParsePlaceAlgorithm {
}

std::vector<std::string> default_choices() {
return {"bounding_box", "criticality_timing", "slack_timing"};
return {"bounding_box", "criticality_timing", "slack_timing", "congestion_aware"};
}
};

Expand Down Expand Up @@ -1432,6 +1448,10 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
.help("Show this help message then exit")
.action(argparse::Action::HELP);

gen_grp.add_argument(args.top_mod, "--top", "-t")
.help("Top module name")
.default_value("");

gen_grp.add_argument<bool, ParseOnOff>(args.show_version, "--version")
.help("Show version information then exit")
.action(argparse::Action::VERSION);
Expand Down Expand Up @@ -1909,6 +1929,16 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
.default_value("semiDirectedSwap")
.show_in(argparse::ShowIn::HELP_ONLY);

pack_grp.add_argument<bool, ParseOnOff>(args.use_partitioning_in_pack, "--use_partitioning_in_pack")
.help("Whether to use partitioning in pack.")
.default_value("off")
.show_in(argparse::ShowIn::HELP_ONLY);

pack_grp.add_argument<int>(args.number_of_molecules_in_partition, "--number_of_molecules_in_partition")
.help("Average number of molecules in each cluster. It should be used when --use_partitioning_in_pack is on.")
.default_value("64")
.show_in(argparse::ShowIn::HELP_ONLY);

auto& place_grp = parser.add_argument_group("placement options");

place_grp.add_argument(args.Seed, "--seed")
Expand Down Expand Up @@ -2014,7 +2044,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
" * criticality_timing: Focuses on minimizing both the wirelength and the connection timing costs (criticality * delay).\n"
" * slack_timing: Focuses on improving the circuit slack values to reduce critical path delay.\n")
.default_value("criticality_timing")
.choices({"bounding_box", "criticality_timing", "slack_timing"})
.choices({"bounding_box", "criticality_timing", "slack_timing", "congestion_aware"})
.show_in(argparse::ShowIn::HELP_ONLY);

place_grp.add_argument<e_place_algorithm, ParsePlaceAlgorithm>(args.PlaceQuenchAlgorithm, "--place_quench_algorithm")
Expand All @@ -2026,7 +2056,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
" * criticality_timing: Focuses on minimizing both the wirelength and the connection timing costs (criticality * delay).\n"
" * slack_timing: Focuses on improving the circuit slack values to reduce critical path delay.\n")
.default_value("criticality_timing")
.choices({"bounding_box", "criticality_timing", "slack_timing"})
.choices({"bounding_box", "criticality_timing", "slack_timing", "congestion_aware"})
.show_in(argparse::ShowIn::HELP_ONLY);

place_grp.add_argument(args.PlaceChanWidth, "--place_chan_width")
Expand Down Expand Up @@ -2064,6 +2094,14 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
.default_value("false")
.show_in(argparse::ShowIn::HELP_ONLY);

// Cascade Placer
place_grp.add_argument(args.enable_cascade_placer, "--enable_cascade_placer")
.help(
"Enables the cascade placer. "
"Once analytic placement is done, the result is passed through the annealing (SA) placer")
.default_value("false")
.show_in(argparse::ShowIn::HELP_ONLY);

place_grp.add_argument(args.place_static_move_prob, "--place_static_move_prob")
.help(
"The percentage probabilities of different moves in Simulated Annealing placement. "
Expand Down
94 changes: 42 additions & 52 deletions include/packer_fix/post_routing_pb_pin_fixup.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ static bool check_pb_route_for_block(ClusterBlockId clb_id,
PB_route_error& err) {
err.reset();
err.clb_id_ = clb_id;
err.clbLoc_ = plCon.block_locs[clb_id];
err.clbLoc_ = plCon.block_locs()[clb_id];

const t_pb& clb = *clCon.clb_nlist.block_pb(clb_id);
VTR_ASSERT(clb.name);
Expand Down Expand Up @@ -260,7 +260,7 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li
* Deposit all the sides
*/
if (wanted_sides.empty()) {
for (e_side side : {TOP, BOTTOM, LEFT, RIGHT}) {
for (e_side side : TOTAL_2D_SIDES) {
wanted_sides.push_back(side);
}
}
Expand Down Expand Up @@ -309,55 +309,49 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li
ParentNetId routing_net_id = ParentNetId::INVALID();
std::vector<RRNodeId> visited_rr_nodes;
short valid_routing_net_cnt = 0;
int addToY = 0, addToX = 0;
addToY = physical_tile->height;
addToX = physical_tile->width;
for (int ix = 0; ix < addToX; ix++) {
for (int iy = 0; iy < addToY; iy++) {
for (const e_side& pin_side : pin_sides) {
/* Find the net mapped to this pin in routing results */
RRNodeId rr_node = node_lookup.find_node(coord_layer, coord_x + ix, coord_y + iy, rr_node_type, physical_pin, pin_side);

/* Bypass invalid nodes, after that we must have a valid rr_node id */
if (!rr_node) {
continue;
}
VTR_ASSERT((size_t)rr_node < device_ctx.rr_graph.num_nodes());
for (const e_side& pin_side : pin_sides) {
/* Find the net mapped to this pin in routing results */
RRNodeId rr_node = node_lookup.find_node(coord_layer, coord_x, coord_y, rr_node_type, physical_pin, pin_side);

/* If the node has been visited on the other side, we just skip it */
if (visited_rr_nodes.end() != std::find(visited_rr_nodes.begin(), visited_rr_nodes.end(), RRNodeId(rr_node))) {
continue;
}
/* Bypass invalid nodes, after that we must have a valid rr_node id */
if (!rr_node) {
continue;
}
VTR_ASSERT((size_t)rr_node < device_ctx.rr_graph.num_nodes());

/* Get the cluster net id which has been mapped to this net
* In general, there is only one valid rr_node among all the sides.
* However, we have an exception in the Stratix-IV arch modeling,
* where a pb_pin may exist in two different sides but
* router will only map to 1 rr_node
* Therefore, it is better to compare the routing nets
* for all the sides and pick
* - The unique valid net id (others should be all invalid)
* assume that this pin is used by router
* - A invalid net id (others should be all invalid as well)
* assume that this pin is not used by router
*/
if (rr_node_nets[rr_node]) {
if (routing_net_id) {
if (routing_net_id != rr_node_nets[rr_node]) {
VTR_LOG_ERROR("Pin '%s' is mapped to two nets: '%s' and '%s'\n",
pb_graph_pin->to_string().c_str(),
net_list.net_name(routing_net_id).c_str(),
net_list.net_name(rr_node_nets[rr_node]).c_str());
}
VTR_ASSERT(routing_net_id == rr_node_nets[rr_node]);
}
routing_net_id = rr_node_nets[rr_node];
valid_routing_net_cnt++;
visited_rr_nodes.push_back(rr_node);
/* If the node has been visited on the other side, we just skip it */
if (visited_rr_nodes.end() != std::find(visited_rr_nodes.begin(), visited_rr_nodes.end(), RRNodeId(rr_node))) {
continue;
}

/* Get the cluster net id which has been mapped to this net
* In general, there is only one valid rr_node among all the sides.
* However, we have an exception in the Stratix-IV arch modeling,
* where a pb_pin may exist in two different sides but
* router will only map to 1 rr_node
* Therefore, it is better to compare the routing nets
* for all the sides and pick
* - The unique valid net id (others should be all invalid)
* assume that this pin is used by router
* - A invalid net id (others should be all invalid as well)
* assume that this pin is not used by router
*/
if (rr_node_nets[rr_node]) {
if (routing_net_id) {
if (routing_net_id != rr_node_nets[rr_node]) {
VTR_LOG_ERROR("Pin '%s' is mapped to two nets: '%s' and '%s'\n",
pb_graph_pin->to_string().c_str(),
net_list.net_name(routing_net_id).c_str(),
net_list.net_name(rr_node_nets[rr_node]).c_str());
}
VTR_ASSERT(routing_net_id == rr_node_nets[rr_node]);
}
routing_net_id = rr_node_nets[rr_node];
valid_routing_net_cnt++;
visited_rr_nodes.push_back(rr_node);
}
}

VTR_ASSERT((0 == valid_routing_net_cnt) || (1 == valid_routing_net_cnt));

/* Find the net mapped to this pin in clustering results*/
Expand Down Expand Up @@ -935,8 +929,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom
*/
VTR_ASSERT(sink_pb_route == sink_pb_pin_to_add->pin_count_in_cluster);
t_pb_graph_pin* new_sink_pb_pin_to_add = sink_pb_pin_to_add;
//VTR_ASSERT(is_single_fanout_pb_pin(const_cast<const t_pb_graph_pin*>(new_sink_pb_pin_to_add)));
VTR_ASSERT(new_sink_pb_pin_to_add->output_edges[0]->num_output_pins == 1);
VTR_ASSERT(is_single_fanout_pb_pin(const_cast<const t_pb_graph_pin*>(new_sink_pb_pin_to_add)));
int new_driver_pb_pin = pb_graph_pin->pin_count_in_cluster;
while (1) {
int new_sink_pb_route_id = new_sink_pb_pin_to_add->pin_count_in_cluster;
Expand Down Expand Up @@ -1045,7 +1038,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom
for (int& sink_pb_route : new_pb_route.sink_pb_pin_ids) {
usedItems.push_back(sink_pb_route);
}

VTR_LOGV(verbose,
"Remap clustered block '%s' routing trace[%d] to net '%s'\n",
clustering_ctx.clb_nlist.block_pb(blk_id)->name,
Expand Down Expand Up @@ -1264,18 +1257,15 @@ void sync_netlists_to_routing(const Netlist<>& net_list,
clb_blk_id = convert_to_cluster_block_id(blk_id);
}
VTR_ASSERT(clb_blk_id != ClusterBlockId::INVALID());
// vtr::Point<size_t> grid_coord(placement_ctx.block_locs[clb_blk_id].loc.x,
// placement_ctx.block_locs[clb_blk_id].loc.y);

if (seen_block_ids.insert(clb_blk_id).second) {
update_cluster_pin_with_post_routing_results(net_list,
atom_ctx,
device_ctx,
clustering_ctx,
rr_node_nets,
placement_ctx.block_locs[clb_blk_id].loc,
placement_ctx.block_locs()[clb_blk_id].loc,
clb_blk_id,
// placement_ctx.block_locs[clb_blk_id].loc.sub_tile,
num_mismatches,
verbose,
is_flat);
Expand Down
2 changes: 1 addition & 1 deletion planning/src/main.cpp
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
static const char* _pln_VERSION_STR = "pln0350";
static const char* _pln_VERSION_STR = "pln0351";

#include "RS/rsEnv.h"
#include "util/pln_log.h"
Expand Down
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