Skip to content

Adding support for multi-bit constants in IO primitives' port connections #814

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 6 commits into from
Oct 31, 2024
Merged

Adding support for multi-bit constants in IO primitives' port connections #814

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
213def7
Adding support for multibit constants
behzadmehmood Oct 30, 2024
820d4f3
Merge branch 'main' of https://github.com/os-fpga/yosys_verific_rs in…
behzadmehmood Oct 31, 2024
eef4768
Merge branch 'main' of https://github.com/os-fpga/yosys_verific_rs in…
behzadmehmood Oct 31, 2024
aa5567c
Incremented patch version
behzadmehmood Oct 31, 2024
3a000f7
Adding code comment
behzadmehmood Oct 31, 2024
93e9e16
Merge branch 'bug/EDA-3307/multi_bit_consts' of https://github.com/os…
behzadmehmood Oct 31, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ set(VERSION_MINOR 0)



set(VERSION_PATCH 379)
set(VERSION_PATCH 380)



Expand Down
41 changes: 28 additions & 13 deletions design_edit/src/rs_design_edit.cc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1566,6 +1566,8 @@ struct DesignEditRapidSilicon : public ScriptPass {
for (auto conn : cell->connections()) {
IdString portName = conn.first;
RTLIL::SigSpec actual = conn.second;
bool unset_port = true;
RTLIL::SigSpec sigspec;
if (actual.is_chunk()) {
RTLIL::Wire *wire = actual.as_chunk().wire;
if (wire != NULL) {
Expand All @@ -1585,19 +1587,6 @@ struct DesignEditRapidSilicon : public ScriptPass {
}
}
}
} else {
RTLIL::SigSpec const_sig = actual;
if (GetSize(const_sig) != 0)
{
RTLIL::SigSig new_conn;
RTLIL::Wire *new_wire = original_mod->addWire(NEW_ID, GetSize(const_sig));
cell->unsetPort(portName);
cell->setPort(portName, new_wire);
new_conn.first = new_wire;
new_conn.second = const_sig;
original_mod->connect(new_conn);
process_wire(cell, portName, new_wire);
}
}
} else {
for (auto it = actual.chunks().rbegin();
Expand All @@ -1623,6 +1612,32 @@ struct DesignEditRapidSilicon : public ScriptPass {
}
}
}
for (SigBit bit : conn.second)
{
// Route constant bits through fabric
if (bit.wire == nullptr)
{
if (unset_port)
{
cell->unsetPort(portName);
unset_port = false;
}
RTLIL::SigSig new_conn;
RTLIL::Wire *new_wire = original_mod->addWire(NEW_ID, 1);
new_conn.first = new_wire;
new_conn.second = bit;
original_mod->connect(new_conn);
new_outs.insert(new_wire->name.str());
sigspec.append(new_wire);
} else {
sigspec.append(bit);
}
}

if (!unset_port)
{
cell->setPort(portName, sigspec);
}
}
} else {
for (auto conn : cell->connections()) {
Expand Down
Loading