Use report_edges instead

Author: akashlevy

test/liberty_arcs_one2one.ok

@@ -1,18 +1,60 @@
 Warning: liberty_arcs_one2one.lib line 48, timing port A and related port Y are different sizes.
 Warning: liberty_arcs_one2one.lib line 76, timing port A and related port Y are different sizes.
 TEST 1:
-Startpoint                           Endpoint                               Slack
---------------------------------------------------------------------------------
-a[0] (input)                         y[0] (output)                          -1.00
-a[1] (input)                         y[1] (output)                          -1.00
-a[2] (input)                         y[2] (output)                          -1.00
-a[3] (input)                         y[3] (output)                          -1.00
-
+report_edges -from partial_wide_inv_cell/A[0]
+A[0] -> Y[0] combinational
+  v -> v 1.00:1.00
+  ^ -> v 1.00:1.00
+  ^ -> ^ 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[1]
+A[1] -> Y[1] combinational
+  v -> v 1.00:1.00
+  ^ -> v 1.00:1.00
+  ^ -> ^ 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[2]
+A[2] -> Y[2] combinational
+  v -> v 1.00:1.00
+  ^ -> v 1.00:1.00
+  ^ -> ^ 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[3]
+A[3] -> Y[3] combinational
+  v -> v 1.00:1.00
+  ^ -> v 1.00:1.00
+  ^ -> ^ 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[4]
+report_edges -from partial_wide_inv_cell/A[5]
+report_edges -from partial_wide_inv_cell/A[6]
+report_edges -from partial_wide_inv_cell/A[7]
 TEST 2:
-Startpoint                           Endpoint                               Slack
---------------------------------------------------------------------------------
-a[0] (input)                         y[0] (output)                          -1.00
-a[1] (input)                         y[1] (output)                          -1.00
-a[2] (input)                         y[2] (output)                          -1.00
-a[3] (input)                         y[3] (output)                          -1.00
-
+report_edges -to partial_wide_inv_cell/Y[0]
+A[0] -> Y[0] combinational
+  v -> v 1.00:1.00
+  ^ -> v 1.00:1.00
+  ^ -> ^ 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -to partial_wide_inv_cell/Y[1]
+A[1] -> Y[1] combinational
+  v -> v 1.00:1.00
+  ^ -> v 1.00:1.00
+  ^ -> ^ 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -to partial_wide_inv_cell/Y[2]
+A[2] -> Y[2] combinational
+  v -> v 1.00:1.00
+  ^ -> v 1.00:1.00
+  ^ -> ^ 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -to partial_wide_inv_cell/Y[3]
+A[3] -> Y[3] combinational
+  v -> v 1.00:1.00
+  ^ -> v 1.00:1.00
+  ^ -> ^ 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -to partial_wide_inv_cell/Y[4]
+report_edges -to partial_wide_inv_cell/Y[5]
+report_edges -to partial_wide_inv_cell/Y[6]
+report_edges -to partial_wide_inv_cell/Y[7]

test/liberty_arcs_one2one.tcl

@@ -6,12 +6,18 @@ link_design liberty_arcs_one2one_1
 create_clock -name clk -period 0
 set_input_delay -clock clk 0 [all_inputs]
 set_output_delay -clock clk 0 [all_outputs]
-report_checks -format summary -group_count 5
+for {set i 0} {$i < 8} {incr i} {
+    puts "report_edges -from partial_wide_inv_cell/A[$i]"
+    report_edges -from partial_wide_inv_cell/A[$i]
+}
 
 puts "TEST 2:"
 read_verilog liberty_arcs_one2one_2.v
 link_design liberty_arcs_one2one_2
 create_clock -name clk -period 0
 set_input_delay -clock clk 0 [all_inputs]
 set_output_delay -clock clk 0 [all_outputs]
-report_checks -format summary -group_count 5
+for {set i 0} {$i < 8} {incr i} {
+    puts "report_edges -to partial_wide_inv_cell/Y[$i]"
+    report_edges -to partial_wide_inv_cell/Y[$i]
+}