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akashlevyakashlevy
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Smallfix to get tests consistently passing in regression
1 parent f54ab5b commit f77647a

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‎test/liberty_arcs_one2one.ok‎

Lines changed: 12 additions & 214 deletions
Original file line numberDiff line numberDiff line change
@@ -1,220 +1,18 @@
11
Warning: liberty_arcs_one2one.lib line 48, timing port A and related port Y are different sizes.
22
Warning: liberty_arcs_one2one.lib line 76, timing port A and related port Y are different sizes.
33
TEST 1:
4-
Startpoint: a[0] (input port clocked by clk)
5-
Endpoint: y[0] (output port clocked by clk)
6-
Path Group: clk
7-
Path Type: max
8-
9-
Delay Time Description
10-
---------------------------------------------------------
11-
0.00 0.00 clock clk (rise edge)
12-
0.00 0.00 clock network delay (ideal)
13-
0.00 0.00 v input external delay
14-
0.00 0.00 v a[0] (in)
15-
1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_8_to_4)
16-
0.00 1.00 ^ y[0] (out)
17-
1.00 data arrival time
18-
19-
0.00 0.00 clock clk (rise edge)
20-
0.00 0.00 clock network delay (ideal)
21-
0.00 0.00 clock reconvergence pessimism
22-
0.00 0.00 output external delay
23-
0.00 data required time
24-
---------------------------------------------------------
25-
0.00 data required time
26-
-1.00 data arrival time
27-
---------------------------------------------------------
28-
-1.00 slack (VIOLATED)
29-
30-
31-
Startpoint: a[1] (input port clocked by clk)
32-
Endpoint: y[1] (output port clocked by clk)
33-
Path Group: clk
34-
Path Type: max
35-
36-
Delay Time Description
37-
---------------------------------------------------------
38-
0.00 0.00 clock clk (rise edge)
39-
0.00 0.00 clock network delay (ideal)
40-
0.00 0.00 v input external delay
41-
0.00 0.00 v a[1] (in)
42-
1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_8_to_4)
43-
0.00 1.00 ^ y[1] (out)
44-
1.00 data arrival time
45-
46-
0.00 0.00 clock clk (rise edge)
47-
0.00 0.00 clock network delay (ideal)
48-
0.00 0.00 clock reconvergence pessimism
49-
0.00 0.00 output external delay
50-
0.00 data required time
51-
---------------------------------------------------------
52-
0.00 data required time
53-
-1.00 data arrival time
54-
---------------------------------------------------------
55-
-1.00 slack (VIOLATED)
56-
57-
58-
Startpoint: a[2] (input port clocked by clk)
59-
Endpoint: y[2] (output port clocked by clk)
60-
Path Group: clk
61-
Path Type: max
62-
63-
Delay Time Description
64-
---------------------------------------------------------
65-
0.00 0.00 clock clk (rise edge)
66-
0.00 0.00 clock network delay (ideal)
67-
0.00 0.00 v input external delay
68-
0.00 0.00 v a[2] (in)
69-
1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_8_to_4)
70-
0.00 1.00 ^ y[2] (out)
71-
1.00 data arrival time
72-
73-
0.00 0.00 clock clk (rise edge)
74-
0.00 0.00 clock network delay (ideal)
75-
0.00 0.00 clock reconvergence pessimism
76-
0.00 0.00 output external delay
77-
0.00 data required time
78-
---------------------------------------------------------
79-
0.00 data required time
80-
-1.00 data arrival time
81-
---------------------------------------------------------
82-
-1.00 slack (VIOLATED)
83-
84-
85-
Startpoint: a[3] (input port clocked by clk)
86-
Endpoint: y[3] (output port clocked by clk)
87-
Path Group: clk
88-
Path Type: max
89-
90-
Delay Time Description
91-
---------------------------------------------------------
92-
0.00 0.00 clock clk (rise edge)
93-
0.00 0.00 clock network delay (ideal)
94-
0.00 0.00 v input external delay
95-
0.00 0.00 v a[3] (in)
96-
1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_8_to_4)
97-
0.00 1.00 ^ y[3] (out)
98-
1.00 data arrival time
99-
100-
0.00 0.00 clock clk (rise edge)
101-
0.00 0.00 clock network delay (ideal)
102-
0.00 0.00 clock reconvergence pessimism
103-
0.00 0.00 output external delay
104-
0.00 data required time
105-
---------------------------------------------------------
106-
0.00 data required time
107-
-1.00 data arrival time
108-
---------------------------------------------------------
109-
-1.00 slack (VIOLATED)
110-
4+
Startpoint Endpoint Slack
5+
--------------------------------------------------------------------------------
6+
a[0] (input) y[0] (output) -1.00
7+
a[1] (input) y[1] (output) -1.00
8+
a[2] (input) y[2] (output) -1.00
9+
a[3] (input) y[3] (output) -1.00
11110

11211
TEST 2:
113-
Startpoint: a[0] (input port clocked by clk)
114-
Endpoint: y[0] (output port clocked by clk)
115-
Path Group: clk
116-
Path Type: max
117-
118-
Delay Time Description
119-
---------------------------------------------------------
120-
0.00 0.00 clock clk (rise edge)
121-
0.00 0.00 clock network delay (ideal)
122-
0.00 0.00 v input external delay
123-
0.00 0.00 v a[0] (in)
124-
1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_4_to_8)
125-
0.00 1.00 ^ y[0] (out)
126-
1.00 data arrival time
127-
128-
0.00 0.00 clock clk (rise edge)
129-
0.00 0.00 clock network delay (ideal)
130-
0.00 0.00 clock reconvergence pessimism
131-
0.00 0.00 output external delay
132-
0.00 data required time
133-
---------------------------------------------------------
134-
0.00 data required time
135-
-1.00 data arrival time
136-
---------------------------------------------------------
137-
-1.00 slack (VIOLATED)
138-
139-
140-
Startpoint: a[1] (input port clocked by clk)
141-
Endpoint: y[1] (output port clocked by clk)
142-
Path Group: clk
143-
Path Type: max
144-
145-
Delay Time Description
146-
---------------------------------------------------------
147-
0.00 0.00 clock clk (rise edge)
148-
0.00 0.00 clock network delay (ideal)
149-
0.00 0.00 v input external delay
150-
0.00 0.00 v a[1] (in)
151-
1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_4_to_8)
152-
0.00 1.00 ^ y[1] (out)
153-
1.00 data arrival time
154-
155-
0.00 0.00 clock clk (rise edge)
156-
0.00 0.00 clock network delay (ideal)
157-
0.00 0.00 clock reconvergence pessimism
158-
0.00 0.00 output external delay
159-
0.00 data required time
160-
---------------------------------------------------------
161-
0.00 data required time
162-
-1.00 data arrival time
163-
---------------------------------------------------------
164-
-1.00 slack (VIOLATED)
165-
166-
167-
Startpoint: a[2] (input port clocked by clk)
168-
Endpoint: y[2] (output port clocked by clk)
169-
Path Group: clk
170-
Path Type: max
171-
172-
Delay Time Description
173-
---------------------------------------------------------
174-
0.00 0.00 clock clk (rise edge)
175-
0.00 0.00 clock network delay (ideal)
176-
0.00 0.00 v input external delay
177-
0.00 0.00 v a[2] (in)
178-
1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_4_to_8)
179-
0.00 1.00 ^ y[2] (out)
180-
1.00 data arrival time
181-
182-
0.00 0.00 clock clk (rise edge)
183-
0.00 0.00 clock network delay (ideal)
184-
0.00 0.00 clock reconvergence pessimism
185-
0.00 0.00 output external delay
186-
0.00 data required time
187-
---------------------------------------------------------
188-
0.00 data required time
189-
-1.00 data arrival time
190-
---------------------------------------------------------
191-
-1.00 slack (VIOLATED)
192-
193-
194-
Startpoint: a[3] (input port clocked by clk)
195-
Endpoint: y[3] (output port clocked by clk)
196-
Path Group: clk
197-
Path Type: max
198-
199-
Delay Time Description
200-
---------------------------------------------------------
201-
0.00 0.00 clock clk (rise edge)
202-
0.00 0.00 clock network delay (ideal)
203-
0.00 0.00 v input external delay
204-
0.00 0.00 v a[3] (in)
205-
1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_4_to_8)
206-
0.00 1.00 ^ y[3] (out)
207-
1.00 data arrival time
208-
209-
0.00 0.00 clock clk (rise edge)
210-
0.00 0.00 clock network delay (ideal)
211-
0.00 0.00 clock reconvergence pessimism
212-
0.00 0.00 output external delay
213-
0.00 data required time
214-
---------------------------------------------------------
215-
0.00 data required time
216-
-1.00 data arrival time
217-
---------------------------------------------------------
218-
-1.00 slack (VIOLATED)
219-
12+
Startpoint Endpoint Slack
13+
--------------------------------------------------------------------------------
14+
a[0] (input) y[0] (output) -1.00
15+
a[1] (input) y[1] (output) -1.00
16+
a[2] (input) y[2] (output) -1.00
17+
a[3] (input) y[3] (output) -1.00
22018

‎test/liberty_arcs_one2one.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,12 +6,12 @@ link_design liberty_arcs_one2one_1
66
create_clock -name clk -period 0
77
set_input_delay -clock clk 0 [all_inputs]
88
set_output_delay -clock clk 0 [all_outputs]
9-
report_checks -group_count 5
9+
report_checks -format summary -group_count 5
1010

1111
puts "TEST 2:"
1212
read_verilog liberty_arcs_one2one_2.v
1313
link_design liberty_arcs_one2one_2
1414
create_clock -name clk -period 0
1515
set_input_delay -clock clk 0 [all_inputs]
1616
set_output_delay -clock clk 0 [all_outputs]
17-
report_checks -group_count 5
17+
report_checks -format summary -group_count 5

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