Merging master into rtm4

Author: Daniel McLean

.gitignore

@@ -12,18 +12,47 @@
 *.swo
 *.eep
 *.elf
+*.la
+*.lo
 *.lss
+*.log
 *.sym
 *.cproject
 *.project
 *.settings*
 */Debug/*
 *.sw?
+*.in
+*.cache
+*.guess
+*.sub
+*.m4
+.deps
+.libs
 .metadata/*
 RemoteSystemsTempFiles/*
 boot/.dep/*
-tags
 out/*
+tags
+ar-lib
+compile
+configure
+depcomp
+Makefile
+missing
+libtool
+ltmain.sh
+install-sh
+
+#Ignore output binaries
+mcu
+mem
+server
+
+#Ignore generated headers
+config.status
+config.h
+stamp-h1
 
 #Ignore hex (programming files) in this directory
 *.hex

autogen.sh

@@ -29,6 +29,7 @@ if [ "$1" = "clean" ]; then
       -o -name 'ltsugar.m4' \
       -o -name 'ltversion.m4' \
       -o -name 'lt~obsolete.m4' \
+      -o -name 'm4' \
       -o -name 'missing' \
       -o -name 'stamp-h1' \
       -o -name 'test-driver' \

common/common.c

@@ -17,79 +17,45 @@
 
 #include "common.h"
 
-static FILE* fout = NULL;
-static FILE* dout = NULL;
+int verbose;
 
-int PRINT( print_t priority, const char* format, ... ) {
-	int ret = 0;
-	va_list args;
-	va_start(args, format);
+void PRINT_WRAPPER( print_t priority, const char* format, ... ) {
 
-	// open the file
-	if (!fout) {
-		fout = fopen(LOG_FILE, "a");
-	}
+	FILE* o;
 
-	if (!dout) {
-		dout = fopen(DUMP_FILE, "a");
-	}
+	va_list args;
+	va_start( args, format );
 
-	// get the time
-	struct timespec ts;
-	clock_gettime(CLOCK_REALTIME, &ts);
+	o = NULL;
 
-	// pre-pend the print message with time and info
-	char newfmt[BUF_SIZE] = {0};
-	switch (priority) {
+	switch( priority ){
 		case ERROR:
-			snprintf(newfmt, BUF_SIZE, "[%6ld.%03ld] ERROR: ", (long)ts.tv_sec, ts.tv_nsec / 1000000UL);
+			o = stderr;
 			break;
-		case INFO:
-			snprintf(newfmt, BUF_SIZE, "[%6ld.%03ld] INFO:  ", (long)ts.tv_sec, ts.tv_nsec / 1000000UL);
+
+		case VERBOSE:
+			if ( verbose >= 1 ){
+				o = stdout;
+			}
 			break;
+
 		case DEBUG:
-			snprintf(newfmt, BUF_SIZE, "[%6ld.%03ld] DEBUG: ", (long)ts.tv_sec, ts.tv_nsec / 1000000UL);
-			break;
-		case VERBOSE:
-			snprintf(newfmt, BUF_SIZE, "[%6ld.%03ld] VERB:  ", (long)ts.tv_sec, ts.tv_nsec / 1000000UL);
+			if ( verbose >= 2 ){
+				o = stdout;
+			}
 			break;
+
+		case INFO:
 		case DUMP:
-			snprintf(newfmt, BUF_SIZE, "[%6ld.%03ld] DUMP:  ", (long)ts.tv_sec, ts.tv_nsec / 1000000UL);
-			break;
 		default:
-			snprintf(newfmt, BUF_SIZE, "[%6ld.%03ld] DFLT:  ", (long)ts.tv_sec, ts.tv_nsec / 1000000UL);
+			o = stdout;
 			break;
 	}
-	strcpy(newfmt + strlen(newfmt), format);
-
-	// DUMP or DEBUG or INFO or ERROR, file
-	if (fout && priority != VERBOSE) {
-		ret = vfprintf(fout, newfmt, args );
-	}
-
-	// INFO, stdout
-	if (priority == INFO) {
-		ret = vprintf(newfmt, args);
-	}
 
-	// ERROR, stderr
-	if (priority == ERROR ) {
-		ret = vfprintf(stderr, newfmt, args );
+	if ( NULL != o ) {
+		vfprintf( o, format, args );
+		fflush( o );
 	}
 
-	// DUMP, file
-	if (priority == DUMP) {
-		ret = vfprintf(dout, newfmt, args);
-	}
-
-	if (priority == VERBOSE) {
-		// do nothing as of now
-	}
-
-	// flush the file
-	fflush(fout);
-	fflush(dout);
-
-	va_end(args);
-	return ret;
+	va_end( args );
 }

common/common.h

@@ -134,7 +134,18 @@ typedef enum {
 } print_t;
 
 // printf wrapper
-int PRINT( print_t priority, const char* format, ... );
+void PRINT_WRAPPER( print_t priority, const char* format, ... );
+
+#define PRINT( prio, fmt, args ... ) \
+	do { \
+		struct timespec _ts;  \
+		clock_gettime( CLOCK_REALTIME, & _ts ); \
+		if ( ERROR == prio ) { \
+			PRINT_WRAPPER( prio, "[%6ld.%03ld] %s: %s(): " fmt, (long)_ts.tv_sec, _ts.tv_nsec / 1000000UL, #prio, __func__, ##args ); \
+		} else { \
+			PRINT_WRAPPER( prio, "[%6ld.%03ld] %s: " fmt, (long)_ts.tv_sec, _ts.tv_nsec / 1000000UL, #prio, ##args ); \
+		} \
+	} while( 0 )
 
 #define LOG_FILE	( "/var/crimson/crimson.log" )
 #define DUMP_FILE	( "/var/crimson/dump.log" )

hal/drivers/mmap/regmap.c

@@ -35,6 +35,11 @@ static const reg_t reg_table[] = {
 	{0x0b0 + HPS2FPGA_GPR_OFST, "sys11",  0x00000000, "RW"},
 	{0x0c0 + HPS2FPGA_GPR_OFST, "sys12",  0x00000000, "RW"},
 	{0x0d0 + HPS2FPGA_GPR_OFST, "sys13",  0x00000000, "RW"},
+	{0x0e0 + HPS2FPGA_GPR_OFST, "sys14",  0x00000000, "RO"},
+	{0x0f0 + HPS2FPGA_GPR_OFST, "sys15",  0x00000000, "RO"},
+	{0x0f4 + HPS2FPGA_GPR_OFST, "sys16",  0x00000000, "RO"},
+	{0x0f8 + HPS2FPGA_GPR_OFST, "sys17",  0x00000000, "RO"},
+	{0x0fc + HPS2FPGA_GPR_OFST, "sys18",  0x00000000, "RO"},
 
 
 	{0x120 + HPS2FPGA_GPR_OFST, "led0",  0x00000000, "RW"},
@@ -80,6 +85,10 @@ static const reg_t reg_table[] = {
 	{0x460 + HPS2FPGA_GPR_OFST, "rxa6", 0x00000000, "RW"},
 	{0x470 + HPS2FPGA_GPR_OFST, "rxa7", 0x00000000, "RW"},
 	{0x480 + HPS2FPGA_GPR_OFST, "rxa8", 0x0000a745, "RW"},
+	{0x484 + HPS2FPGA_GPR_OFST, "rxa9", 0x00000000, "RW"},
+	{0x488 + HPS2FPGA_GPR_OFST, "rxa10", 0x00000000, "RW"},
+	{0x48c + HPS2FPGA_GPR_OFST, "rxa11", 0x00000000, "RW"},
+	{0x490 + HPS2FPGA_GPR_OFST, "rxa12", 0x00000000, "RW"},
 	{0x500 + HPS2FPGA_GPR_OFST, "rxb0", 0x00000000, "RW"},
 	{0x510 + HPS2FPGA_GPR_OFST, "rxb1", 0x000000ff, "RW"},
 	{0x520 + HPS2FPGA_GPR_OFST, "rxb2", 0x00000000, "RW"},
@@ -89,6 +98,10 @@ static const reg_t reg_table[] = {
 	{0x560 + HPS2FPGA_GPR_OFST, "rxb6", 0x00000000, "RW"},
 	{0x570 + HPS2FPGA_GPR_OFST, "rxb7", 0x00000000, "RW"},
 	{0x580 + HPS2FPGA_GPR_OFST, "rxb8", 0x0000a746, "RW"},
+	{0x584 + HPS2FPGA_GPR_OFST, "rxb9", 0x00000000, "RW"},
+	{0x588 + HPS2FPGA_GPR_OFST, "rxb10", 0x00000000, "RW"},
+	{0x58c + HPS2FPGA_GPR_OFST, "rxb11", 0x00000000, "RW"},
+	{0x590 + HPS2FPGA_GPR_OFST, "rxb12", 0x00000000, "RW"},
 	{0x600 + HPS2FPGA_GPR_OFST, "rxc0", 0x00000000, "RW"},
 	{0x610 + HPS2FPGA_GPR_OFST, "rxc1", 0x000000ff, "RW"},
 	{0x620 + HPS2FPGA_GPR_OFST, "rxc2", 0x00000000, "RW"},
@@ -98,6 +111,10 @@ static const reg_t reg_table[] = {
 	{0x660 + HPS2FPGA_GPR_OFST, "rxc6", 0x00000000, "RW"},
 	{0x670 + HPS2FPGA_GPR_OFST, "rxc7", 0x00000000, "RW"},
 	{0x680 + HPS2FPGA_GPR_OFST, "rxc8", 0x0000a747, "RW"},
+	{0x684 + HPS2FPGA_GPR_OFST, "rxc9", 0x00000000, "RW"},
+	{0x688 + HPS2FPGA_GPR_OFST, "rxc10", 0x00000000, "RW"},
+	{0x68c + HPS2FPGA_GPR_OFST, "rxc11", 0x00000000, "RW"},
+	{0x690 + HPS2FPGA_GPR_OFST, "rxc12", 0x00000000, "RW"},
 	{0x700 + HPS2FPGA_GPR_OFST, "rxd0", 0x00000000, "RW"},
 	{0x710 + HPS2FPGA_GPR_OFST, "rxd1", 0x000000ff, "RW"},
 	{0x720 + HPS2FPGA_GPR_OFST, "rxd2", 0x00000000, "RW"},
@@ -107,31 +124,51 @@ static const reg_t reg_table[] = {
 	{0x760 + HPS2FPGA_GPR_OFST, "rxd6", 0x00000000, "RW"},
 	{0x770 + HPS2FPGA_GPR_OFST, "rxd7", 0x00000000, "RW"},
 	{0x780 + HPS2FPGA_GPR_OFST, "rxd8", 0x0000a748, "RW"},
+	{0x784 + HPS2FPGA_GPR_OFST, "rxd9", 0x00000000, "RW"},
+	{0x788 + HPS2FPGA_GPR_OFST, "rxd10", 0x00000000, "RW"},
+	{0x78c + HPS2FPGA_GPR_OFST, "rxd11", 0x00000000, "RW"},
+	{0x790 + HPS2FPGA_GPR_OFST, "rxd12", 0x00000000, "RW"},
 
 	{0x800 + HPS2FPGA_GPR_OFST, "txa0", 0x00000000, "RW"},
 	{0x810 + HPS2FPGA_GPR_OFST, "txa1", 0x000000ff, "RW"},
 	{0x820 + HPS2FPGA_GPR_OFST, "txa2", 0x00000000, "RW"},
 	{0x830 + HPS2FPGA_GPR_OFST, "txa3", 0x00000000, "RW"},
 	{0x840 + HPS2FPGA_GPR_OFST, "txa4", 0x00000000, "RW"},
 	{0x850 + HPS2FPGA_GPR_OFST, "txa5", 0x0000a749, "RW"},
+	{0x854 + HPS2FPGA_GPR_OFST, "txa6", 0x00000000, "RW"},
+	{0x858 + HPS2FPGA_GPR_OFST, "txa7", 0x00000000, "RW"},
+	{0x85c + HPS2FPGA_GPR_OFST, "txa8", 0x00000000, "RW"},
+	{0x860 + HPS2FPGA_GPR_OFST, "txa9", 0x00000000, "RW"},
 	{0x900 + HPS2FPGA_GPR_OFST, "txb0", 0x00000000, "RW"},
 	{0x910 + HPS2FPGA_GPR_OFST, "txb1", 0x000000ff, "RW"},
 	{0x920 + HPS2FPGA_GPR_OFST, "txb2", 0x00000000, "RW"},
 	{0x930 + HPS2FPGA_GPR_OFST, "txb3", 0x00000000, "RW"},
 	{0x940 + HPS2FPGA_GPR_OFST, "txb4", 0x00000200, "RW"},
 	{0x950 + HPS2FPGA_GPR_OFST, "txb5", 0x0000a74a, "RW"},
+	{0x954 + HPS2FPGA_GPR_OFST, "txb6", 0x00000000, "RW"},
+	{0x958 + HPS2FPGA_GPR_OFST, "txb7", 0x00000000, "RW"},
+	{0x95c + HPS2FPGA_GPR_OFST, "txb8", 0x00000000, "RW"},
+	{0x960 + HPS2FPGA_GPR_OFST, "txb9", 0x00000000, "RW"},
 	{0xa00 + HPS2FPGA_GPR_OFST, "txc0", 0x00000000, "RW"},
 	{0xa10 + HPS2FPGA_GPR_OFST, "txc1", 0x000000ff, "RW"},
 	{0xa20 + HPS2FPGA_GPR_OFST, "txc2", 0x00000000, "RW"},
 	{0xa30 + HPS2FPGA_GPR_OFST, "txc3", 0x00000000, "RW"},
 	{0xa40 + HPS2FPGA_GPR_OFST, "txc4", 0x00000000, "RW"},
 	{0xa50 + HPS2FPGA_GPR_OFST, "txc5", 0x0000a74b, "RW"},
+	{0xa54 + HPS2FPGA_GPR_OFST, "txc6", 0x00000000, "RW"},
+	{0xa58 + HPS2FPGA_GPR_OFST, "txc7", 0x00000000, "RW"},
+	{0xa5c + HPS2FPGA_GPR_OFST, "txc8", 0x00000000, "RW"},
+	{0xa60 + HPS2FPGA_GPR_OFST, "txc9", 0x00000000, "RW"},
 	{0xb00 + HPS2FPGA_GPR_OFST, "txd0", 0x00000000, "RW"},
 	{0xb10 + HPS2FPGA_GPR_OFST, "txd1", 0x000000ff, "RW"},
 	{0xb20 + HPS2FPGA_GPR_OFST, "txd2", 0x00000000, "RW"},
 	{0xb30 + HPS2FPGA_GPR_OFST, "txd3", 0x00000000, "RW"},
 	{0xb40 + HPS2FPGA_GPR_OFST, "txd4", 0x00000200, "RW"},
 	{0xb50 + HPS2FPGA_GPR_OFST, "txd5", 0x0000a74c, "RW"},
+	{0xb54 + HPS2FPGA_GPR_OFST, "txd6", 0x00000000, "RW"},
+	{0xb58 + HPS2FPGA_GPR_OFST, "txd7", 0x00000000, "RW"},
+	{0xb5c + HPS2FPGA_GPR_OFST, "txd8", 0x00000000, "RW"},
+	{0xb60 + HPS2FPGA_GPR_OFST, "txd9", 0x00000000, "RW"},
 
 	{0xc00 + HPS2FPGA_GPR_OFST, "rxga", 0x80808080, "RW"},
 	{0xc10 + HPS2FPGA_GPR_OFST, "txga", 0x80808080, "RW"},

hal/pllcalc.c

@@ -46,14 +46,14 @@ int main (void)
         pllparam_t pll;
 
         //Debug parameters;
-        double max_diff = 5000001;
+        double max_diff = PLL_CORE_REF_FREQ_HZ/PLL1_R_FIXED;
         double max_N = PLL1_N_MAX;
         double max_R = PLL1_R_MAX;
         int printdebug = 0;
         uint64_t stepFreq = (1000000);
 
         //for (reqFreq = stepFreq * 100; reqFreq <= stepFreq * 6250; reqFreq += stepFreq)
-	for (reqFreq = 2600000000; reqFreq <= 2900000000; reqFreq += stepFreq)
+	for (reqFreq = 700e6; reqFreq <= 6800000000; reqFreq += stepFreq)
         {
 
                 // This is the main function, everything after is for statistics
@@ -191,11 +191,12 @@ double setFreq(uint64_t* reqFreq, pllparam_t* pll) {
 
         // 2. Use the reference to determine R, N, and pfd frequency
        long double pd_freq = (long double)PLL_CORE_REF_FREQ_HZ / (long double)pll->R;
-	
 
         double N1 = 0;
+
         // Determine the values of the N and dividers for PLL1
         if ( !pll->divFBen || *reqFreq < PLL1_FB_THRESHOLD ) {
+            pll->divFBen = 0;
             N1  = (double)pll->vcoFreq / (double)pd_freq;
         } else {
             N1  = (double)pll->vcoFreq / (double)pll->d;

hal/pllcalc.h

@@ -76,10 +76,10 @@
 // ADF4355 Default specs
 #define PLL1_R_FIXED		( 13 )		// R value must be fixed to ensure consistent PFD frequency (13MHz)
 
-#define PLL1_N_DEFAULT		( 572 )         // N value (N^2 contribution to PLL noise) [16..4096]
+#define PLL1_N_DEFAULT		( 112 )         // N value (N^2 contribution to PLL noise) [16..4096]
 #define PLL1_D_DEFAULT		( 2 )		// RFoutput divider value (1,2,4,6..58,60,62)
 #define PLL1_X2EN_DEFAULT	( 0 )           // RFoutput doubler enabled (0=off, 1=on (RFout is doubled))
-#define PLL1_OUTFREQ_DEFAULT	( 2904700000 )	// Resulting VCO Output Frequency
+#define PLL1_OUTFREQ_DEFAULT	( 2800000000 )	// Resulting VCO Output Frequency
 #define PLL1_FB_DEFAULT         ( 0 )           // VCO divider feedback