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Adding enumeration for btleldoctrl register. (#390)
* Adding enumeration for btleldoctrl register. * Adding new bit fields. * Moving bit fields. Adding trim register. * Fixing bit offset for LDORXVSEL. * Fixing copyright year. * Adding SIR BTLE LDO trim register. * ME17: Added deprecated attributes into SVD file. * ME17: Removed field definitions from max32655.h. * ME20: Resolving dependent SVD file changes. * AI85/ME20: Resolved dependent SVD file changes. --------- Co-authored-by: Kevin Gillespie <[email protected]> Co-authored-by: Sihyung Woo <[email protected]> MSDK-Commit: 0eb794ddc2b799e1ffb614283d10abe578a567ed
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lines changed

‎MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h‎

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
*/
66

77
/******************************************************************************
8-
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
8+
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
99
*
1010
* Permission is hereby granted, free of charge, to any person obtaining a
1111
* copy of this software and associated documentation files (the "Software"),
@@ -699,6 +699,17 @@ typedef struct {
699699
#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */
700700
#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */
701701

702+
#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */
703+
#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */
704+
#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Value */
705+
#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Setting */
706+
#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Value */
707+
#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Setting */
708+
#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Value */
709+
#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Setting */
710+
#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Value */
711+
#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Setting */
712+
702713
#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS 2 /**< BTLELDOCTRL_LDOTXVSEL0 Position */
703714
#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS)) /**< BTLELDOCTRL_LDOTXVSEL0 Mask */
704715

@@ -711,6 +722,17 @@ typedef struct {
711722
#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */
712723
#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */
713724

725+
#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */
726+
#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */
727+
#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORXVSEL_0_7 Value */
728+
#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_7 Setting */
729+
#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORXVSEL_0_85 Value */
730+
#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_85 Setting */
731+
#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORXVSEL_0_9 Value */
732+
#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_9 Setting */
733+
#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORXVSEL_1_1 Value */
734+
#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_1_1 Setting */
735+
714736
#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS 6 /**< BTLELDOCTRL_LDORXVSEL0 Position */
715737
#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS)) /**< BTLELDOCTRL_LDORXVSEL0 Mask */
716738

‎MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd‎

Lines changed: 70 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -3806,16 +3806,32 @@
38063806
<bitWidth>1</bitWidth>
38073807
</field>
38083808
<field>
3809-
<name>LDOTXVSEL0</name>
3809+
<name>LDOTXVSEL</name>
38103810
<description>LDOTX Voltage Setting.</description>
38113811
<bitOffset>2</bitOffset>
3812-
<bitWidth>1</bitWidth>
3813-
</field>
3814-
<field>
3815-
<name>LDOTXVSEL1</name>
3816-
<description>LDOTX Voltage Setting.</description>
3817-
<bitOffset>3</bitOffset>
3818-
<bitWidth>1</bitWidth>
3812+
<bitWidth>2</bitWidth>
3813+
<enumeratedValues>
3814+
<enumeratedValue>
3815+
<name>0_7</name>
3816+
<description>0.7V</description>
3817+
<value>0</value>
3818+
</enumeratedValue>
3819+
<enumeratedValue>
3820+
<name>0_85</name>
3821+
<description>0.85V</description>
3822+
<value>1</value>
3823+
</enumeratedValue>
3824+
<enumeratedValue>
3825+
<name>0_9</name>
3826+
<description>0.9V</description>
3827+
<value>2</value>
3828+
</enumeratedValue>
3829+
<enumeratedValue>
3830+
<name>1_1</name>
3831+
<description>1.1V</description>
3832+
<value>3</value>
3833+
</enumeratedValue>
3834+
</enumeratedValues>
38193835
</field>
38203836
<field>
38213837
<name>LDORXEN</name>
@@ -3830,16 +3846,32 @@
38303846
<bitWidth>1</bitWidth>
38313847
</field>
38323848
<field>
3833-
<name>LDORXVSEL0</name>
3849+
<name>LDORXVSEL</name>
38343850
<description>LDORX Voltage Setting.</description>
38353851
<bitOffset>6</bitOffset>
3836-
<bitWidth>1</bitWidth>
3837-
</field>
3838-
<field>
3839-
<name>LDORXVSEL1</name>
3840-
<description>LDORX Voltage Setting.</description>
3841-
<bitOffset>7</bitOffset>
3842-
<bitWidth>1</bitWidth>
3852+
<bitWidth>2</bitWidth>
3853+
<enumeratedValues>
3854+
<enumeratedValue>
3855+
<name>0_7</name>
3856+
<description>0.7V</description>
3857+
<value>0</value>
3858+
</enumeratedValue>
3859+
<enumeratedValue>
3860+
<name>0_85</name>
3861+
<description>0.85V</description>
3862+
<value>1</value>
3863+
</enumeratedValue>
3864+
<enumeratedValue>
3865+
<name>0_9</name>
3866+
<description>0.9V</description>
3867+
<value>2</value>
3868+
</enumeratedValue>
3869+
<enumeratedValue>
3870+
<name>1_1</name>
3871+
<description>1.1V</description>
3872+
<value>3</value>
3873+
</enumeratedValue>
3874+
</enumeratedValues>
38433875
</field>
38443876
<field>
38453877
<name>LDORXBYP</name>
@@ -9058,6 +9090,28 @@
90589090
</field>
90599091
</fields>
90609092
</register>
9093+
<register>
9094+
<name>BTLE_LDO_TRIM</name>
9095+
<description>BTLE LDO Trim register.</description>
9096+
<addressOffset>0x48</addressOffset>
9097+
<access>read-write</access>
9098+
<fields>
9099+
<field>
9100+
<name>TX</name>
9101+
<description>TX LDO trim value.</description>
9102+
<bitOffset>0</bitOffset>
9103+
<bitWidth>5</bitWidth>
9104+
<access>read-write</access>
9105+
</field>
9106+
<field>
9107+
<name>RX</name>
9108+
<description>RX LDO trim value.</description>
9109+
<bitOffset>8</bitOffset>
9110+
<bitWidth>5</bitWidth>
9111+
<access>read-write</access>
9112+
</field>
9113+
</fields>
9114+
</register>
90619115
<register>
90629116
<name>FSTAT</name>
90639117
<description>funcstat register.</description>

‎MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h‎

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
*/
66

77
/******************************************************************************
8-
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
8+
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
99
*
1010
* Permission is hereby granted, free of charge, to any person obtaining a
1111
* copy of this software and associated documentation files (the "Software"),
@@ -88,7 +88,9 @@ extern "C" {
8888
typedef struct {
8989
__I uint32_t sistat; /**< <tt>\b 0x00:</tt> SIR SISTAT Register */
9090
__I uint32_t addr; /**< <tt>\b 0x04:</tt> SIR ADDR Register */
91-
__R uint32_t rsv_0x8_0xff[62];
91+
__R uint32_t rsv_0x8_0x47[16];
92+
__IO uint32_t btle_ldo_trim; /**< <tt>\b 0x48:</tt> SIR BTLE_LDO_TRIM Register */
93+
__R uint32_t rsv_0x4c_0xff[45];
9294
__I uint32_t fstat; /**< <tt>\b 0x100:</tt> SIR FSTAT Register */
9395
__I uint32_t sfstat; /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */
9496
} mxc_sir_regs_t;
@@ -102,6 +104,7 @@ typedef struct {
102104
*/
103105
#define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */
104106
#define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */
107+
#define MXC_R_SIR_BTLE_LDO_TRIM ((uint32_t)0x00000048UL) /**< Offset from SIR Base Address: <tt> 0x0048</tt> */
105108
#define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */
106109
#define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */
107110
/**@} end of group sir_registers */
@@ -133,6 +136,20 @@ typedef struct {
133136

134137
/**@} end of group SIR_ADDR_Register */
135138

139+
/**
140+
* @ingroup sir_registers
141+
* @defgroup SIR_BTLE_LDO_TRIM SIR_BTLE_LDO_TRIM
142+
* @brief BTLE LDO Trim register.
143+
* @{
144+
*/
145+
#define MXC_F_SIR_BTLE_LDO_TRIM_TX_POS 0 /**< BTLE_LDO_TRIM_TX Position */
146+
#define MXC_F_SIR_BTLE_LDO_TRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_POS)) /**< BTLE_LDO_TRIM_TX Mask */
147+
148+
#define MXC_F_SIR_BTLE_LDO_TRIM_RX_POS 8 /**< BTLE_LDO_TRIM_RX Position */
149+
#define MXC_F_SIR_BTLE_LDO_TRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_POS)) /**< BTLE_LDO_TRIM_RX Mask */
150+
151+
/**@} end of group SIR_BTLE_LDO_TRIM_Register */
152+
136153
/**
137154
* @ingroup sir_registers
138155
* @defgroup SIR_FSTAT SIR_FSTAT

‎MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h‎

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
*/
66

77
/******************************************************************************
8-
* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
8+
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
99
*
1010
* Permission is hereby granted, free of charge, to any person obtaining a
1111
* copy of this software and associated documentation files (the "Software"),
@@ -699,6 +699,17 @@ typedef struct {
699699
#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */
700700
#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */
701701

702+
#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */
703+
#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */
704+
#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Value */
705+
#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Setting */
706+
#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Value */
707+
#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Setting */
708+
#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Value */
709+
#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Setting */
710+
#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Value */
711+
#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Setting */
712+
702713
#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS 2 /**< BTLELDOCTRL_LDOTXVSEL0 Position */
703714
#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS)) /**< BTLELDOCTRL_LDOTXVSEL0 Mask */
704715

@@ -711,6 +722,17 @@ typedef struct {
711722
#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */
712723
#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */
713724

725+
#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */
726+
#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */
727+
#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORXVSEL_0_7 Value */
728+
#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_7 Setting */
729+
#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORXVSEL_0_85 Value */
730+
#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_85 Setting */
731+
#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORXVSEL_0_9 Value */
732+
#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_9 Setting */
733+
#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORXVSEL_1_1 Value */
734+
#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_1_1 Setting */
735+
714736
#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS 6 /**< BTLELDOCTRL_LDORXVSEL0 Position */
715737
#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS)) /**< BTLELDOCTRL_LDORXVSEL0 Mask */
716738

‎MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd‎

Lines changed: 70 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -3806,16 +3806,32 @@
38063806
<bitWidth>1</bitWidth>
38073807
</field>
38083808
<field>
3809-
<name>LDOTXVSEL0</name>
3809+
<name>LDOTXVSEL</name>
38103810
<description>LDOTX Voltage Setting.</description>
38113811
<bitOffset>2</bitOffset>
3812-
<bitWidth>1</bitWidth>
3813-
</field>
3814-
<field>
3815-
<name>LDOTXVSEL1</name>
3816-
<description>LDOTX Voltage Setting.</description>
3817-
<bitOffset>3</bitOffset>
3818-
<bitWidth>1</bitWidth>
3812+
<bitWidth>2</bitWidth>
3813+
<enumeratedValues>
3814+
<enumeratedValue>
3815+
<name>0_7</name>
3816+
<description>0.7V</description>
3817+
<value>0</value>
3818+
</enumeratedValue>
3819+
<enumeratedValue>
3820+
<name>0_85</name>
3821+
<description>0.85V</description>
3822+
<value>1</value>
3823+
</enumeratedValue>
3824+
<enumeratedValue>
3825+
<name>0_9</name>
3826+
<description>0.9V</description>
3827+
<value>2</value>
3828+
</enumeratedValue>
3829+
<enumeratedValue>
3830+
<name>1_1</name>
3831+
<description>1.1V</description>
3832+
<value>3</value>
3833+
</enumeratedValue>
3834+
</enumeratedValues>
38193835
</field>
38203836
<field>
38213837
<name>LDORXEN</name>
@@ -3830,16 +3846,32 @@
38303846
<bitWidth>1</bitWidth>
38313847
</field>
38323848
<field>
3833-
<name>LDORXVSEL0</name>
3849+
<name>LDORXVSEL</name>
38343850
<description>LDORX Voltage Setting.</description>
38353851
<bitOffset>6</bitOffset>
3836-
<bitWidth>1</bitWidth>
3837-
</field>
3838-
<field>
3839-
<name>LDORXVSEL1</name>
3840-
<description>LDORX Voltage Setting.</description>
3841-
<bitOffset>7</bitOffset>
3842-
<bitWidth>1</bitWidth>
3852+
<bitWidth>2</bitWidth>
3853+
<enumeratedValues>
3854+
<enumeratedValue>
3855+
<name>0_7</name>
3856+
<description>0.7V</description>
3857+
<value>0</value>
3858+
</enumeratedValue>
3859+
<enumeratedValue>
3860+
<name>0_85</name>
3861+
<description>0.85V</description>
3862+
<value>1</value>
3863+
</enumeratedValue>
3864+
<enumeratedValue>
3865+
<name>0_9</name>
3866+
<description>0.9V</description>
3867+
<value>2</value>
3868+
</enumeratedValue>
3869+
<enumeratedValue>
3870+
<name>1_1</name>
3871+
<description>1.1V</description>
3872+
<value>3</value>
3873+
</enumeratedValue>
3874+
</enumeratedValues>
38433875
</field>
38443876
<field>
38453877
<name>LDORXBYP</name>
@@ -9058,6 +9090,28 @@
90589090
</field>
90599091
</fields>
90609092
</register>
9093+
<register>
9094+
<name>BTLE_LDO_TRIM</name>
9095+
<description>BTLE LDO Trim register.</description>
9096+
<addressOffset>0x48</addressOffset>
9097+
<access>read-write</access>
9098+
<fields>
9099+
<field>
9100+
<name>TX</name>
9101+
<description>TX LDO trim value.</description>
9102+
<bitOffset>0</bitOffset>
9103+
<bitWidth>5</bitWidth>
9104+
<access>read-write</access>
9105+
</field>
9106+
<field>
9107+
<name>RX</name>
9108+
<description>RX LDO trim value.</description>
9109+
<bitOffset>8</bitOffset>
9110+
<bitWidth>5</bitWidth>
9111+
<access>read-write</access>
9112+
</field>
9113+
</fields>
9114+
</register>
90619115
<register>
90629116
<name>FSTAT</name>
90639117
<description>funcstat register.</description>

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