Add verilator simulation #28
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Being able to simulate the whole processor using Verilator is a powerful tool. I feel like others could benefit from having a simple example of simulation using Verilator contained within the repository, to complement the simulation of individual modules using iverilog.
I've added a Makefile and all the necessary files to simulate the processor using Verilator.
I wasn't sure whether this should be submitted as a pull request to this repository, or to the f-of-e-tools repository. I can change it so that it is on f-of-e-tools instead if that would be preferable.
I'd appreciate your comments and feedback!