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@CheeksTheGeek CheeksTheGeek commented Nov 10, 2025

Resolves #164

  • implements the first pattern from https://vlsi-soc.blogspot.com/2013/06/dual-edge-triggered-flip-flop.html
    • is only allowed on explicit allowance based on --allow-dual-edge-ff
    • 2 FFs + mux
    • simply put, (posedge ff --> intermediary --> negedge FF --> intermediary) mux selects on these based on clock
    • also an async reset impl for this
    • Made sure to use helpers, similar to canvas->addDff and canvas->addAldff for the dual edge versions

cc: @povik @whitequark

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codecov bot commented Nov 10, 2025

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 66.85%. Comparing base (f449089) to head (bf83b74).

Additional details and impacted files
@@            Coverage Diff             @@
##           master     #245      +/-   ##
==========================================
+ Coverage   66.17%   66.85%   +0.68%     
==========================================
  Files          18       18              
  Lines        5602     5696      +94     
  Branches     1256     1262       +6     
==========================================
+ Hits         3707     3808     +101     
+ Misses       1486     1483       -3     
+ Partials      409      405       -4     

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See comment; I've also pushed a functional test to your branch


// Synthesizes two single-edge FFs (one posedge, one negedge) with the same D input,
// then uses a mux controlled by the clock to select the appropriate FF output.
static void add_dual_edge_dff(NetlistContext &netlist, const ast::ProceduralBlockSymbol &symbol,
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Please move this to builder.cc and merge it with the async load version

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Support for dual-edge FFs always (@edge clk)

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