handle simple assignments patterns on left-hand-side (lhs)

src/slang_frontend.cc

@@ -1349,6 +1349,19 @@ RTLIL::SigSpec SignalEvalContext::lhs(const ast::Expression &expr)
 											expr.type->getBitstreamWidth());
 		}
 		break;
+	case ast::ExpressionKind::SimpleAssignmentPattern:
+		{
+			const ast::SimpleAssignmentPatternExpression &pattern_expr = expr.as<ast::SimpleAssignmentPatternExpression>();
+			for (auto op : pattern_expr.elements())
+				ret = {ret, lhs(*op)};
+		}
+		break;
+	case ast::ExpressionKind::Assignment:
+		{
+			const ast::AssignmentExpression &ae = expr.as<ast::AssignmentExpression>();
+			ret = lhs(ae.left());
+		}
+		break;
 	default:
 		unimplemented(expr);
 		break;

tests/various/simple_assignment_pattern_lhs.sv

@@ -0,0 +1,12 @@
+module top();
+
+logic [31:0]data[4] = '{ 4 { 32'hdeadbeef } };
+
+logic [31:0]a, b, c, d;
+
+// should allow mismatched size
+//assign '{ {a[15:0], b[31:16]}, { b[15:0], a[31:24] }, c, d } = data;
+
+assign '{ {a[15:0], b[31:16]}, { b[15:0], a[31:16] }, c, d } = data;
+
+endmodule

tests/various/simple_assignment_pattern_lhs.ys

@@ -0,0 +1 @@
+read_slang simple_assignment_pattern_lhs.sv