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Port: Add PMU cycle counting for Armv8.1-M #909
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CBMC Results (ML-DSA-87)Full Results (173 proofs)
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CBMC Results (ML-DSA-44)Full Results (173 proofs)
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CBMC Results (ML-DSA-65)Full Results (173 proofs)
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Thanks @willieyz. You unintentionally changed the default benchmarking parameters - probably because you copied them from mlkem-native - we cannot use the same paramters as for mlkem-native. Besides that two other nits.
I will fix both myself shortly.
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Thanks @willieyz. I fixed it myself.
Note: The benchmarking parameters for the mps3-an547 are really small. Too small to produce cycle counts for signing that are reasonably close to the expected value due to the rejection sampling. However, otherwise the benchmarks take forever. For key generation and verification, we have verified that cycles are reasonably stable, close to what we get with larger iteration counts, and benchmarking complete in less than 30 seconds on the MPS3 FPGA. For proper benchmarks of signing one will have to use much larger values.
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Make the benchmark parameters (NWARMUP, NITERATIONS, NTESTS) configurable via CFLAGS by wrapping them in #ifndef guards and renaming to MLD_BENCHMARK_NWARMUP, MLD_BENCHMARK_NITERATIONS, and MLD_BENCHMARK_NTESTS. Signed-off-by: willieyz <[email protected]>
Add PMU-based cycle counting support for Armv8.1-M Cortex-M processors. This uses the CMSIS PMU APIs for portable cycle counter access. Signed-off-by: willieyz <[email protected]>
The cycle counts will be zero, but it still tests the PMU code builds. Signed-off-by: willieyz <[email protected]>
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Ported from pq-code-package/mlkem-native#1514, adding PMU-based cycle counting support for Armv8.1-M Cortex-M processors and aligning the RISC-V PMU configuration in hal.c with mlkem-native.