Skip to content

[RV64_DYNAREC] Refactored opcode prefix decoding #3282

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
ptitSeb merged 2 commits into from
Dec 16, 2025
Merged

[RV64_DYNAREC] Refactored opcode prefix decoding #3282

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
1915e44
[RV64_DYNAREC] Refactored opcode prefix decoding
ksco Dec 16, 2025
05e85b1
more
ksco Dec 16, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 0 additions & 6 deletions CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1031,12 +1031,7 @@ if(RV64_DYNAREC)
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_00_3.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_0f.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_0f_vector.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_64.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_64_vector.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_66.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_67.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_67_vector.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_67_32.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_d8.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_d9.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_da.c"
Expand All @@ -1051,7 +1046,6 @@ if(RV64_DYNAREC)
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_660f_vector.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_66f20f.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_66f30f.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_6664.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_66f0.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_f20f.c"
"${BOX64_ROOT}/src/dynarec/rv64/dynarec_rv64_f20f_vector.c"
Expand Down
29 changes: 0 additions & 29 deletions src/dynarec/dynarec_native_pass.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -192,7 +192,6 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
}
#endif

#if defined (ARM64) || defined (LA64)
uint8_t pk = PK(0);

rex.rex = 0;
Expand Down Expand Up @@ -234,34 +233,6 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
addr = dynarec64_66(dyn, addr, ip, ninst, rex, &ok, &need_epilog);
else
addr = dynarec64_00(dyn, addr, ip, ninst, rex, &ok, &need_epilog);
#else
rep = 0;
rex.is32bits = is32bits;
uint8_t pk = PK(0);
while((pk==0xF2) || (pk==0xF3) || (pk==0x3E) || (pk==0x26)
|| (is32bits && ((pk==0x2E) || (pk==0x36)))
) {
switch(pk) {
case 0xF2: rep = 1; break;
case 0xF3: rep = 2; break;
case 0x2E:
case 0x36:
case 0x3E:
case 0x26: /* ignored */ break;
}
++addr;
pk = PK(0);
}
rex.rex = 0;
if(!rex.is32bits)
while(pk>=0x40 && pk<=0x4f) {
rex.rex = pk;
++addr;
pk = PK(0);
}

addr = dynarec64_00(dyn, addr, ip, ninst, rex, rep, &ok, &need_epilog);
#endif
if(dyn->abort)
return ip;
INST_EPILOG;
Expand Down
10 changes: 5 additions & 5 deletions src/dynarec/rv64/dynarec_rv64_00.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -23,16 +23,16 @@
#include "dynarec_rv64_functions.h"
#include "../dynarec_helper.h"

uintptr_t dynarec64_00(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
uintptr_t dynarec64_00(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
{
uint8_t opcode;

opcode = PK(0);
switch (opcode) {
case 0x00 ... 0x3f: addr = dynarec64_00_0(dyn, addr, ip, ninst, rex, rep, ok, need_epilog); break;
case 0x40 ... 0x7f: addr = dynarec64_00_1(dyn, addr, ip, ninst, rex, rep, ok, need_epilog); break;
case 0x80 ... 0xbf: addr = dynarec64_00_2(dyn, addr, ip, ninst, rex, rep, ok, need_epilog); break;
case 0xc0 ... 0xff: addr = dynarec64_00_3(dyn, addr, ip, ninst, rex, rep, ok, need_epilog); break;
case 0x00 ... 0x3f: addr = dynarec64_00_0(dyn, addr, ip, ninst, rex, ok, need_epilog); break;
case 0x40 ... 0x7f: addr = dynarec64_00_1(dyn, addr, ip, ninst, rex, ok, need_epilog); break;
case 0x80 ... 0xbf: addr = dynarec64_00_2(dyn, addr, ip, ninst, rex, ok, need_epilog); break;
case 0xc0 ... 0xff: addr = dynarec64_00_3(dyn, addr, ip, ninst, rex, ok, need_epilog); break;
}

return addr;
Expand Down
4 changes: 2 additions & 2 deletions src/dynarec/rv64/dynarec_rv64_00_0.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@
#include "dynarec_rv64_functions.h"
#include "../dynarec_helper.h"

uintptr_t dynarec64_00_0(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
uintptr_t dynarec64_00_0(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
{
uint8_t nextop, opcode;
uint8_t gd, ed;
Expand Down Expand Up @@ -212,7 +212,7 @@ uintptr_t dynarec64_00_0(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
}
break;
case 0x0F:
switch (rep) {
switch (rex.rep) {
case 0:
if (cpuext.vector)
retaddr = dynarec64_0F_vector(dyn, addr, ip, ninst, rex, ok, need_epilog);
Expand Down
24 changes: 1 addition & 23 deletions src/dynarec/rv64/dynarec_rv64_00_1.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@

int isSimpleWrapper(wrapper_t fun);

uintptr_t dynarec64_00_1(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
uintptr_t dynarec64_00_1(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
{
uint8_t nextop, opcode;
uint8_t gd, ed, tmp1, tmp2, tmp3;
Expand Down Expand Up @@ -202,28 +202,6 @@ uintptr_t dynarec64_00_1(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
}
}
break;
case 0x64:
if (cpuext.vector)
retaddr = dynarec64_64_vector(dyn, addr, ip, ninst, rex, rep, _FS, ok, need_epilog);
addr = retaddr ? retaddr : dynarec64_64(dyn, addr, ip, ninst, rex, rep, _FS, ok, need_epilog);
break;
case 0x65:
if (cpuext.vector)
retaddr = dynarec64_64_vector(dyn, addr, ip, ninst, rex, rep, _GS, ok, need_epilog);
addr = retaddr ? retaddr : dynarec64_64(dyn, addr, ip, ninst, rex, rep, _GS, ok, need_epilog);
break;
case 0x66:
addr = dynarec64_66(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
break;
case 0x67:
if (rex.is32bits)
addr = dynarec64_67_32(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
else {
if (cpuext.vector)
retaddr = dynarec64_67_vector(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
addr = retaddr ? retaddr : dynarec64_67(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
}
break;
case 0x68:
INST_NAME("PUSH Id");
i64 = F32S;
Expand Down
Loading
Loading