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[LA64_DYNAREC] Fixed a potential issue of the ADDxREGy macro ([RV64_DYNAREC] too) #3284

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Merged
ptitSeb merged 1 commit into from
Dec 16, 2025
Merged

[LA64_DYNAREC] Fixed a potential issue of the ADDxREGy macro ([RV64_DYNAREC] too) #3284

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8 changes: 4 additions & 4 deletions src/dynarec/la64/dynarec_la64_00.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1599,7 +1599,7 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SMREADLOCK(lock);
Expand All @@ -1617,7 +1617,7 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SMREADLOCK(lock);
Expand All @@ -1634,7 +1634,7 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
ST_B(xRAX, x1, 0);
Expand All @@ -1651,7 +1651,7 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SDxw(xRAX, x1, 0);
Expand Down
4 changes: 2 additions & 2 deletions src/dynarec/la64/dynarec_la64_66.c
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Original file line number Diff line number Diff line change
Expand Up @@ -802,7 +802,7 @@ uintptr_t dynarec64_66(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SMREADLOCK(lock);
Expand All @@ -820,7 +820,7 @@ uintptr_t dynarec64_66(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
ST_H(xRAX, x1, 0);
Expand Down
2 changes: 1 addition & 1 deletion src/dynarec/la64/dynarec_la64_helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -231,7 +231,7 @@ uintptr_t geted(dynarec_la64_t* dyn, uintptr_t addr, int ninst, uint8_t nextop,
SCRATCH_USAGE(1);
grab_segdata(dyn, addr, ninst, scratch, rex.seg, 0);
// seg offset is 64bits, so no truncation here
ADDxREGy(hint, scratch, ret);
ADDxREGy(hint, scratch, ret, hint);
ret = hint;
}
*ed = ret;
Expand Down
6 changes: 3 additions & 3 deletions src/dynarec/la64/la64_emitter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2570,11 +2570,11 @@ LSX instruction starts with V, LASX instruction starts with XV.
ADD_D(rd, rj, rk); \
} while (0)

#define ADDxREGy(rd, rj, rk) \
#define ADDxREGy(rd, rj, rk, s1) \
do { \
if (rex.is32bits || rex.is67) { \
ADDI_W(rk, rk, 0); \
ADD_D(rd, rj, rk); \
ADDI_W(s1, rk, 0); \
ADD_D(rd, rj, s1); \
} else \
ADD_D(rd, rj, rk); \
} while (0)
Expand Down
8 changes: 4 additions & 4 deletions src/dynarec/rv64/dynarec_rv64_00_2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -644,7 +644,7 @@ uintptr_t dynarec64_00_2(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SMREADLOCK(lock);
Expand All @@ -663,7 +663,7 @@ uintptr_t dynarec64_00_2(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SMREADLOCK(lock);
Expand All @@ -680,7 +680,7 @@ uintptr_t dynarec64_00_2(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SB(xRAX, x1, 0);
Expand All @@ -697,7 +697,7 @@ uintptr_t dynarec64_00_2(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SDxw(xRAX, x1, 0);
Expand Down
4 changes: 2 additions & 2 deletions src/dynarec/rv64/dynarec_rv64_66.c
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Original file line number Diff line number Diff line change
Expand Up @@ -862,7 +862,7 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SMREADLOCK(lock);
Expand All @@ -880,7 +880,7 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
MOV64y(x1, u64);
if (rex.seg) {
grab_segdata(dyn, addr, ninst, x3, rex.seg, 0);
ADDxREGy(x1, x3, x1);
ADDxREGy(x1, x3, x1, x1);
}
lock = (rex.seg) ? 0 : isLockAddress(u64);
SH(xRAX, x1, 0);
Expand Down
2 changes: 1 addition & 1 deletion src/dynarec/rv64/dynarec_rv64_helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -266,7 +266,7 @@ uintptr_t geted(dynarec_rv64_t* dyn, uintptr_t addr, int ninst, uint8_t nextop,
SCRATCH_USAGE(1);
grab_segdata(dyn, addr, ninst, scratch, rex.seg, 0);
// seg offset is 64bits, so no truncation here
ADDxREGy(hint, scratch, ret);
ADDxREGy(hint, scratch, ret, hint);
ret = hint;
}
*ed = ret;
Expand Down
6 changes: 3 additions & 3 deletions src/dynarec/rv64/rv64_emitter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -134,11 +134,11 @@
ADD(rd, rs1, rs2); \
} \
} while (0)
#define ADDxREGy(rd, rs1, rs2) \
#define ADDxREGy(rd, rs1, rs2, s1) \
do { \
if (rex.is32bits || rex.is67) { \
ADDIW(rs2, rs2, 0); \
ADD(rd, rs1, rs2); \
ADDIW(s1, rs2, 0); \
ADD(rd, rs1, s1); \
} else { \
ADD(rd, rs1, rs2); \
} \
Expand Down
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