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XeratecXeratec
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Implement feedback from Luka
1 parent 7262da8 commit afca596

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11 files changed

+231
-386
lines changed

11 files changed

+231
-386
lines changed

‎Deeploy/Targets/PULPOpen/DMA/L3Dma.py‎

Lines changed: 9 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -12,38 +12,25 @@
1212

1313
class L3DmaFuture(Future):
1414

15-
_initTemplate = NodeTemplate("""
16-
% if comment:
17-
// ${comment}
18-
% endif
19-
pi_cl_ram_req_t ${name} = {0};
20-
21-
""")
15+
_initTemplate = NodeTemplate("pi_cl_ram_req_t ${name} = {0};")
2216

2317
_deinitTemplate = NodeTemplate("")
2418

2519
_allocTemplate = NodeTemplate("")
2620

2721
_waitTemplate = NodeTemplate("""
28-
% if comment:
29-
// ${comment}
30-
% endif
3122
if (${name}.size != 0) {
3223
pi_cl_ram_copy_wait(&${name});
33-
}
34-
""")
24+
}""")
3525

3626

3727
class L3Dma(AsyncDma):
3828

3929
_transferTemplates = {
4030
2:
41-
NodeTemplate("""
42-
% if comment:
43-
// ${comment}
44-
% endif
45-
pi_cl_ram_copy_2d(get_ram_ptr(), ${ext}, ${loc}, ${transfer_size}, ${stride}, ${length}, ${ext2loc}, &${future});
46-
""")
31+
NodeTemplate(
32+
"pi_cl_ram_copy_2d(get_ram_ptr(), ${ext}, ${loc}, ${transfer_size}, ${stride}, ${length}, ${ext2loc}, &${future});"
33+
)
4734
}
4835
_waitingStrategy = PerTensorWaitingStrategy(L3DmaFuture)
4936

@@ -59,17 +46,11 @@ def checkTransfer(self, ctxt: NetworkContext, externalBuffer: VariableBuffer, lo
5946
assert strideLoc[0] == shape[1] and strideLoc[1] == 1, \
6047
f"Mchan supports only contigous transfers for local memory. Received local shape: {shape}, stride: {strideLoc}"
6148

62-
def transferOpRepr(self,
63-
externalBuffer: VariableBuffer,
64-
localBuffer: VariableBuffer,
65-
shape: Tuple[int, ...],
66-
strideExt: Tuple[int, ...],
67-
strideLoc: Tuple[int, ...],
68-
direction: DmaDirection,
69-
future: Future,
70-
comment: str = "") -> OperatorRepresentation:
49+
def transferOpRepr(self, externalBuffer: VariableBuffer, localBuffer: VariableBuffer, shape: Tuple[int, ...],
50+
strideExt: Tuple[int, ...], strideLoc: Tuple[int, ...], direction: DmaDirection,
51+
future: Future) -> OperatorRepresentation:
7152
operatorRepresentation = super().transferOpRepr(externalBuffer, localBuffer, shape, strideExt, strideLoc,
72-
direction, future, comment)
53+
direction, future)
7354
operatorRepresentation.update({
7455
"ext2loc": 1 if direction == "ExternalToLocal" else 0,
7556
"transfer_size": math.prod(shape),

‎Deeploy/Targets/PULPOpen/DMA/MchanDma.py‎

Lines changed: 7 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -11,28 +11,13 @@
1111

1212
class MchanChannelFuture(Future):
1313

14-
_initTemplate = NodeTemplate("""
15-
% if comment:
16-
// ${comment}
17-
% endif
18-
uint32_t ${name} = (uint32_t) -1;
19-
""")
14+
_initTemplate = NodeTemplate("uint32_t ${name} = (uint32_t) -1;")
2015

2116
_deinitTemplate = NodeTemplate("")
2217

23-
_allocTemplate = NodeTemplate("""
24-
% if comment:
25-
// ${comment}
26-
% endif
27-
${name} = mchan_channel_alloc();""")
18+
_allocTemplate = NodeTemplate("${name} = mchan_channel_alloc();")
2819

29-
_waitTemplate = NodeTemplate("""
30-
% if comment:
31-
// ${comment}
32-
% endif
33-
mchan_channel_wait(${name});
34-
mchan_channel_free(${name});
35-
""")
20+
_waitTemplate = NodeTemplate("mchan_channel_wait(${name});\nmchan_channel_free(${name});")
3621

3722

3823
class MchanDma(AsyncDma):
@@ -60,17 +45,11 @@ def checkTransfer(self, ctxt: NetworkContext, externalBuffer: VariableBuffer, lo
6045
assert strideLoc[0] == shape[1] and strideLoc[
6146
1] == 1, "Mchan supports only contigous transfers for local memory"
6247

63-
def transferOpRepr(self,
64-
externalBuffer: VariableBuffer,
65-
localBuffer: VariableBuffer,
66-
shape: Tuple[int, ...],
67-
strideExt: Tuple[int, ...],
68-
strideLoc: Tuple[int, ...],
69-
direction: DmaDirection,
70-
future: Future,
71-
comment: str = "") -> OperatorRepresentation:
48+
def transferOpRepr(self, externalBuffer: VariableBuffer, localBuffer: VariableBuffer, shape: Tuple[int, ...],
49+
strideExt: Tuple[int, ...], strideLoc: Tuple[int, ...], direction: DmaDirection,
50+
future: Future) -> OperatorRepresentation:
7251
operatorRepresentation = super().transferOpRepr(externalBuffer, localBuffer, shape, strideExt, strideLoc,
73-
direction, future, comment)
52+
direction, future)
7453

7554
transferRank = len(shape)
7655

‎Deeploy/Targets/Snitch/CodeTransformationPasses/SnitchClusterTiling.py‎

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,8 @@
44

55
from typing import Tuple
66

7-
from Deeploy.DeeployTypes import CodeGenVerbosity, CodeTransformationPass, ExecutionBlock, NetworkContext, _NoVerbosity
7+
from Deeploy.DeeployTypes import CodeGenVerbosity, CodeTransformationPass, ExecutionBlock, NetworkContext, \
8+
NodeTemplate, _NoVerbosity
89
from Deeploy.TilingExtension.AsyncDma import AsyncDma
910
from Deeploy.TilingExtension.CodeTransformationPasses.DoubleBufferingTilingCodeGeneration import \
1011
DoubleBufferingTilingCodeGeneration, ProfilingDoubleBufferingTilingMixIn
@@ -21,11 +22,17 @@ class SnitchClusterTilingDB(DoubleBufferingTilingCodeGeneration):
2122

2223

2324
class ProfilingSnitchClusterTilingSB(SingleBufferingTilingCodeGeneration, ProfilingSingleBufferingTilingMixIn):
24-
pass
25+
_printCycleDifference = NodeTemplate(r"""
26+
printf("%s%u][Core %d] %s%u%s", ${prefixStr}, ${profileIdxVar}, snrt_global_core_idx(), "${flavorStr}", \
27+
${measurementsEnd}[${profileIdxVar}] - ${measurementsStart}[${profileIdxVar}], ${suffixStr});
28+
""")
2529

2630

2731
class ProfilingSnitchClusterTilingDB(DoubleBufferingTilingCodeGeneration, ProfilingDoubleBufferingTilingMixIn):
28-
pass
32+
_printCycleDifference = NodeTemplate(r"""
33+
printf("%s%u][Core %d] %s%u%s", ${prefixStr}, ${profileIdxVar}, snrt_global_core_idx(), "${flavorStr}", \
34+
${measurementsEnd}[${profileIdxVar}] - ${measurementsStart}[${profileIdxVar}], ${suffixStr});
35+
""")
2936

3037

3138
class SnitchClusterTiling(CodeTransformationPass):

‎Deeploy/Targets/Snitch/DMA/SnitchDma.py‎

Lines changed: 7 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -12,43 +12,26 @@ class SnitchBarrierFuture(Future):
1212
_initTemplate = NodeTemplate("")
1313
_deinitTemplate = NodeTemplate("")
1414
_allocTemplate = NodeTemplate("")
15-
_waitTemplate = NodeTemplate("""
16-
% if comment:
17-
// ${comment}
18-
% endif
19-
if (snrt_is_dm_core()) snrt_dma_wait_all();
20-
""")
15+
_waitTemplate = NodeTemplate("if (snrt_is_dm_core()) snrt_dma_wait_all();")
2116

2217

2318
# LMACAN: TODO: Add single transfer waiting
2419
class SnitchFuture(Future):
25-
_initTemplate = NodeTemplate("""
26-
% if comment:
27-
// ${comment}
28-
% endif
29-
snrt_dma_txid_t ${name} = (snrt_dma_txid_t) -1;
30-
""")
20+
_initTemplate = NodeTemplate("snrt_dma_txid_t ${name} = (snrt_dma_txid_t) -1;")
3121

3222
_deinitTemplate = NodeTemplate("")
3323

3424
_allocTemplate = NodeTemplate("")
3525

36-
_waitTemplate = NodeTemplate("""
37-
% if comment:
38-
// ${comment}
39-
% endif
40-
if ( (${name} != ( (snrt_dma_txid_t) -1) ) && snrt_is_dm_core() ) snrt_dma_wait(${name});
41-
""")
26+
_waitTemplate = NodeTemplate(
27+
"if ( (${name} != ( (snrt_dma_txid_t) -1) ) && snrt_is_dm_core() ) snrt_dma_wait(${name});")
4228

4329

4430
class SnitchDma(AsyncDma):
4531

4632
_transferTemplates = {
4733
2:
4834
NodeTemplate("""
49-
% if comment:
50-
// ${comment}
51-
% endif
5235
if (snrt_is_dm_core()) {
5336
${future} = snrt_dma_start_2d(${dest}, ${src}, ${size}, ${stride_dest}, ${stride_src}, ${repeat});
5437
// WIESEP: Hack as otherwise the last commited DMA transaction ID can never be resolved.
@@ -67,23 +50,16 @@ def checkTransfer(self, ctxt: NetworkContext, externalBuffer: VariableBuffer, lo
6750
super().checkTransfer(ctxt, externalBuffer, localBuffer, shape, strideExt, strideLoc, direction)
6851
assert strideLoc[1] == 1 and strideExt[1] == 1, f"Supports only contigous transfers in the innermost dimension"
6952

70-
def transferOpRepr(self,
71-
externalBuffer: VariableBuffer,
72-
localBuffer: VariableBuffer,
73-
shape: Tuple[int, ...],
74-
strideExt: Tuple[int, ...],
75-
strideLoc: Tuple[int, ...],
76-
direction: DmaDirection,
77-
future: Future,
78-
comment: str = "") -> OperatorRepresentation:
53+
def transferOpRepr(self, externalBuffer: VariableBuffer, localBuffer: VariableBuffer, shape: Tuple[int, ...],
54+
strideExt: Tuple[int, ...], strideLoc: Tuple[int, ...], direction: DmaDirection,
55+
future: Future) -> OperatorRepresentation:
7956
operatorRepresentation: OperatorRepresentation = {
8057
"dest": localBuffer.name if direction == "ExternalToLocal" else externalBuffer.name,
8158
"src": externalBuffer.name if direction == "ExternalToLocal" else localBuffer.name,
8259
"repeat": shape[0],
8360
"size": shape[1],
8461
"stride_dest": strideLoc[0] if direction == "ExternalToLocal" else strideExt[0],
8562
"stride_src": strideExt[0] if direction == "ExternalToLocal" else strideLoc[0],
86-
"comment": comment,
8763
"future": future.name
8864
}
8965
return operatorRepresentation

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