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phsauterphsauter
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hw: replace fetch_en_i with testmode_i
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11 files changed

+21
-60
lines changed

11 files changed

+21
-60
lines changed

‎openroad/src/constraints.sdc‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -83,9 +83,9 @@ set_max_delay 3.0 -from $JTAG_ASYNC_RSP_START -to $JTAG_ASYNC_RSP_END -ignore_cl
8383
puts "Input/Outputs..."
8484

8585
# Reset should propagate to system domain within a clock cycle.
86-
set_input_delay -max [ expr $TCK_JTG * 0.10 ] [get_ports rst_ni]
87-
set_false_path -hold -from [get_ports rst_ni]
88-
set_max_delay $TCK_SYS -from [get_ports rst_ni]
86+
set_input_delay -max [ expr $TCK_JTG * 0.10 ] [get_ports {rst_ni testmode_i}]
87+
set_false_path -hold -from [get_ports {rst_ni testmode_i}]
88+
set_max_delay $TCK_SYS -from [get_ports {rst_ni testmode_i}]
8989

9090

9191
##########
@@ -109,8 +109,8 @@ set_max_delay $TCK_JTG -from [get_ports jtag_trst_ni]
109109
##########
110110
puts "GPIO..."
111111

112-
set_input_delay -min -add_delay -clock clk_sys [ expr $TCK_SYS * 0.10 ] [get_ports {gpio* fetch_en_i}]
113-
set_input_delay -max -add_delay -clock clk_sys [ expr $TCK_SYS * 0.30 ] [get_ports {gpio* fetch_en_i}]
112+
set_input_delay -min -add_delay -clock clk_sys [ expr $TCK_SYS * 0.10 ] [get_ports {gpio*}]
113+
set_input_delay -max -add_delay -clock clk_sys [ expr $TCK_SYS * 0.30 ] [get_ports {gpio*}]
114114

115115
set_output_delay -min -add_delay -clock clk_sys [ expr $TCK_SYS * 0.10 ] [get_ports {gpio*}]
116116
set_output_delay -max -add_delay -clock clk_sys [ expr $TCK_SYS * 0.30 ] [get_ports {gpio*}]

‎openroad/src/padring.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ place_pad -row IO_WEST -location [expr {$westStart - 0*$westPitch}] "pad_vssio0
5050
place_pad -row IO_WEST -location [expr {$westStart - 1*$westPitch}] "pad_vddio0" ; # pin no: 2
5151
place_pad -row IO_WEST -location [expr {$westStart - 2*$westPitch}] "pad_uart_rx_i" ; # pin no: 3
5252
place_pad -row IO_WEST -location [expr {$westStart - 3*$westPitch}] "pad_uart_tx_o" ; # pin no: 4
53-
place_pad -row IO_WEST -location [expr {$westStart - 4*$westPitch}] "pad_fetch_en_i" ; # pin no: 5
53+
place_pad -row IO_WEST -location [expr {$westStart - 4*$westPitch}] "pad_testmode_i" ; # pin no: 5
5454
place_pad -row IO_WEST -location [expr {$westStart - 5*$westPitch}] "pad_status_o" ; # pin no: 6
5555
place_pad -row IO_WEST -location [expr {$westStart - 6*$westPitch}] "pad_clk_i" ; # pin no: 7
5656
place_pad -row IO_WEST -location [expr {$westStart - 7*$westPitch}] "pad_ref_clk_i" ; # pin no: 8

‎rtl/croc_chip.sv‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ module croc_chip import croc_pkg::*; #() (
1919
input wire uart_rx_i,
2020
output wire uart_tx_o,
2121

22-
input wire fetch_en_i,
22+
input wire testmode_i,
2323
output wire status_o,
2424

2525
inout wire gpio0_io,
@@ -67,15 +67,14 @@ module croc_chip import croc_pkg::*; #() (
6767
logic soc_clk_i;
6868
logic soc_rst_ni;
6969
logic soc_ref_clk_i;
70-
logic soc_testmode;
70+
logic soc_testmode_i;
7171

7272
logic soc_jtag_tck_i;
7373
logic soc_jtag_trst_ni;
7474
logic soc_jtag_tms_i;
7575
logic soc_jtag_tdi_i;
7676
logic soc_jtag_tdo_o;
7777

78-
logic soc_fetch_en_i;
7978
logic soc_status_o;
8079

8180
localparam int unsigned GpioCount = 32;
@@ -87,8 +86,6 @@ module croc_chip import croc_pkg::*; #() (
8786
sg13g2_IOPadIn pad_clk_i (.pad(clk_i), .p2c(soc_clk_i));
8887
sg13g2_IOPadIn pad_rst_ni (.pad(rst_ni), .p2c(soc_rst_ni));
8988
sg13g2_IOPadIn pad_ref_clk_i (.pad(ref_clk_i), .p2c(soc_ref_clk_i));
90-
assign soc_testmode_i = '0;
91-
9289
sg13g2_IOPadIn pad_jtag_tck_i (.pad(jtag_tck_i), .p2c(soc_jtag_tck_i));
9390
sg13g2_IOPadIn pad_jtag_trst_ni (.pad(jtag_trst_ni), .p2c(soc_jtag_trst_ni));
9491
sg13g2_IOPadIn pad_jtag_tms_i (.pad(jtag_tms_i), .p2c(soc_jtag_tms_i));
@@ -98,7 +95,7 @@ module croc_chip import croc_pkg::*; #() (
9895
sg13g2_IOPadIn pad_uart_rx_i (.pad(uart_rx_i), .p2c(soc_uart_rx_i));
9996
sg13g2_IOPadOut16mA pad_uart_tx_o (.pad(uart_tx_o), .c2p(soc_uart_tx_o));
10097

101-
sg13g2_IOPadIn pad_fetch_en_i (.pad(fetch_en_i), .p2c(soc_fetch_en_i));
98+
sg13g2_IOPadIn pad_testmode_i (.pad(testmode_i), .p2c(soc_testmode_i));
10299
sg13g2_IOPadOut16mA pad_status_o (.pad(status_o), .c2p(soc_status_o));
103100

104101
sg13g2_IOPadInOut30mA pad_gpio0_io (.pad(gpio0_io), .c2p(soc_gpio_o[0]), .p2c(soc_gpio_i[0]), .c2p_en(soc_gpio_out_en_o[0]));
@@ -166,7 +163,6 @@ module croc_chip import croc_pkg::*; #() (
166163
.rst_ni ( soc_rst_ni ),
167164
.ref_clk_i ( soc_ref_clk_i ),
168165
.testmode_i ( soc_testmode_i ),
169-
.fetch_en_i ( soc_fetch_en_i ),
170166
.status_o ( soc_status_o ),
171167

172168
.jtag_tck_i ( soc_jtag_tck_i ),

‎rtl/croc_domain.sv‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@ module croc_domain import croc_pkg::*; #(
1313
input logic rst_ni,
1414
input logic ref_clk_i,
1515
input logic testmode_i,
16-
input logic fetch_en_i,
1716

1817
input logic jtag_tck_i,
1918
input logic jtag_tdi_i,
@@ -165,7 +164,7 @@ module croc_domain import croc_pkg::*; #(
165164
// Bootrom bus
166165
sbr_obi_req_t bootrom_obi_req;
167166
sbr_obi_rsp_t bootrom_obi_rsp;
168-
167+
169168
// Fanout to individual peripherals
170169
assign error_obi_req = all_periph_obi_req[PeriphError];
171170
assign all_periph_obi_rsp[PeriphError] = error_obi_rsp;
@@ -470,9 +469,6 @@ module croc_domain import croc_pkg::*; #(
470469
);
471470

472471
// SoC Control
473-
logic fetch_en_reg;
474-
assign fetch_enable = fetch_en_i | fetch_en_reg;
475-
476472
soc_ctrl_regs #(
477473
.obi_req_t ( sbr_obi_req_t ),
478474
.obi_rsp_t ( sbr_obi_rsp_t ),
@@ -482,7 +478,7 @@ module croc_domain import croc_pkg::*; #(
482478
.rst_ni,
483479
.obi_req_i ( soc_ctrl_obi_req ),
484480
.obi_rsp_o ( soc_ctrl_obi_rsp ),
485-
.fetch_en_o ( fetch_en_reg ),
481+
.fetch_en_o ( fetch_enable ),
486482
.sram_dly_o ( sram_impl )
487483
);
488484

‎rtl/croc_soc.sv‎

Lines changed: 1 addition & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@ module croc_soc import croc_pkg::*; #(
1212
input logic rst_ni,
1313
input logic ref_clk_i,
1414
input logic testmode_i,
15-
input logic fetch_en_i,
1615
output logic status_o,
1716

1817
input logic jtag_tck_i,
@@ -29,7 +28,7 @@ module croc_soc import croc_pkg::*; #(
2928
output logic [GpioCount-1:0] gpio_out_en_o // Output enable signal; 0 -> input, 1 -> output
3029
);
3130

32-
logic synced_rst_n, synced_fetch_en;
31+
logic synced_rst_n;
3332

3433
rstgen i_rstgen (
3534
.clk_i,
@@ -39,16 +38,6 @@ module croc_soc import croc_pkg::*; #(
3938
.init_no ( )
4039
);
4140

42-
sync #(
43-
.STAGES ( 2 ),
44-
.ResetValue ( 1'b0 )
45-
) i_ext_intr_sync (
46-
.clk_i,
47-
.rst_ni ( synced_rst_n ),
48-
.serial_i ( fetch_en_i ),
49-
.serial_o ( synced_fetch_en )
50-
);
51-
5241
// Connection between Croc_domain and User_domain: User Sbr, Croc Mgr
5342
sbr_obi_req_t user_sbr_obi_req;
5443
sbr_obi_rsp_t user_sbr_obi_rsp;
@@ -69,7 +58,6 @@ croc_domain #(
6958
.rst_ni ( synced_rst_n ),
7059
.ref_clk_i,
7160
.testmode_i,
72-
.fetch_en_i ( synced_fetch_en ),
7361

7462
.jtag_tck_i,
7563
.jtag_tdi_i,

‎rtl/soc_ctrl/soc_ctrl_regs.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ module soc_ctrl_regs #(
118118
always_ff @(posedge clk_i or negedge rst_ni) begin
119119
if (~rst_ni) begin
120120
boot_addr_q <= BootAddrDefault;
121-
fetch_en_q <= '0;
121+
fetch_en_q <= '1;
122122
core_status_q <= '0;
123123
boot_mode_q <= '0;
124124
sram_dly_q <= '0;

‎rtl/test/croc_vip.sv‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@ module croc_vip #(
1212
output logic rst_no,
1313
output logic sys_clk_o,
1414
output logic ref_clk_o,
15-
input logic fetch_en_i,
1615
output logic jtag_tck_o,
1716
output logic jtag_trst_no,
1817
output logic jtag_tms_o,
@@ -334,7 +333,7 @@ module croc_vip #(
334333
initial begin
335334
static byte_bt uart_read_buf[$];
336335
byte_bt bite;
337-
@(posedge fetch_en_i);
336+
@(posedge rst_no);
338337
uart_read_buf.delete();
339338
forever begin
340339
uart_read_byte(bite);

‎rtl/test/tb_croc_soc.sv‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,6 @@ module tb_croc_soc #(
3535
logic [GpioCount-1:0] gpio_out_en;
3636

3737
// Signals controlled by the testbench
38-
logic fetch_en;
3938

4039
/////////////////////////////
4140
// Command Line Arguments //
@@ -73,7 +72,6 @@ module tb_croc_soc #(
7372
.rst_no ( rst_n ),
7473
.sys_clk_o ( sys_clk ),
7574
.ref_clk_o ( ref_clk ),
76-
.fetch_en_i ( fetch_en ),
7775
.jtag_tck_o ( jtag_tck ),
7876
.jtag_trst_no ( jtag_trst_n ),
7977
.jtag_tms_o ( jtag_tms ),
@@ -101,7 +99,6 @@ module tb_croc_soc #(
10199
.rst_ni ( rst_n ),
102100
.ref_clk_i ( ref_clk ),
103101
.testmode_i ( 1'b0 ),
104-
.fetch_en_i ( fetch_en ),
105102
.status_o ( ),
106103
.jtag_tck_i ( jtag_tck ),
107104
.jtag_tdi_i ( jtag_tdi ),
@@ -124,8 +121,6 @@ module tb_croc_soc #(
124121
initial begin
125122
$timeformat(-9, 0, "ns", 12); // 1: scale (ns=-9), 2: decimals, 3: suffix, 4: print-field width
126123

127-
fetch_en = 1'b0;
128-
129124
// wait for reset
130125
#ClkPeriodSys;
131126

@@ -135,9 +130,6 @@ module tb_croc_soc #(
135130
// write test value to sram
136131
i_vip.jtag_write_reg32(SramBaseAddr, 32'h1234_5678, 1'b1);
137132

138-
$display("@%t | [CORE] Start fetching instructions", $time);
139-
fetch_en = 1'b1;
140-
141133
// load binary to sram
142134
i_vip.jtag_load_hex(binary_path);
143135

‎vsim/wave_rtl.do‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ add wave -noupdate -expand -group {Reset & Clocks} -label rst_ni /tb_croc_soc/i
1515
add wave -noupdate -expand -group {Reset & Clocks} -label clk_i /tb_croc_soc/i_croc_soc/clk_i
1616
add wave -noupdate -expand -group {Reset & Clocks} -label ref_clk_i /tb_croc_soc/i_croc_soc/ref_clk_i
1717
add wave -noupdate -expand -group {Mode & Status} -label testmode_i /tb_croc_soc/i_croc_soc/testmode_i
18-
add wave -noupdate -expand -group {Mode & Status} -label fetch_en_i /tb_croc_soc/i_croc_soc/fetch_en_i
1918
add wave -noupdate -expand -group {Mode & Status} -label status_o /tb_croc_soc/i_croc_soc/status_o
2019
add wave -noupdate -expand -group JTAG -label jtag_tck_i /tb_croc_soc/i_croc_soc/jtag_tck_i
2120
add wave -noupdate -expand -group JTAG -label jtag_tdi_i /tb_croc_soc/i_croc_soc/jtag_tdi_i

‎vsim/wave_yosys.do‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@ add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_req_o
2727
add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_rvalid_i
2828
add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_wdata_o
2929
add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_we_o
30-
add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/fetch_enable_i
3130
add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/instr_addr_o
3231
add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/instr_gnt_i
3332
add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/instr_rdata_i

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