rtl: comment vip, simplify wave dump

Author: phsauter

rtl/test/croc_vip.sv

@@ -59,8 +59,8 @@ module croc_vip #(
   //  JTAG  //
   ////////////
 
-  localparam time TApplJtag = 0.2*ClkPeriodJtag;
-  localparam time TTestJtag = 0.8*ClkPeriodJtag;
+  localparam realtime TApplJtag = 0.2*ClkPeriodJtag;
+  localparam realtime TTestJtag = 0.8*ClkPeriodJtag;
   localparam dm::sbcs_t JtagInitSbcs = dm::sbcs_t'{
     sbautoincrement: 1'b1, sbreadondata: 1'b1, sbaccess: 3, default: '0};
 
@@ -278,20 +278,13 @@ module croc_vip #(
   localparam int unsigned ClkFrequency     = 1s / ClkPeriodSys;
   localparam int unsigned UartDivisior     = ClkFrequency / (UartBaudRate*16);
   localparam int unsigned UartRealBaudRate = ClkFrequency / (UartDivisior*16);
-  localparam time         UartBaudPeriod   = 1s / UartRealBaudRate;
+  localparam realtime     UartBaudPeriod   = 1s / UartRealBaudRate;
 
   initial begin
     $display("ClkFrequency: %dMHz", ClkFrequency / 1_000_000);
     $display("UartRealBaudRate: %d", UartRealBaudRate);
   end
 
-  localparam byte_bt UartDebugCmdRead  = 'h11;
-  localparam byte_bt UartDebugCmdWrite = 'h12;
-  localparam byte_bt UartDebugCmdExec  = 'h13;
-  localparam byte_bt UartDebugAck      = 'h06;
-  localparam byte_bt UartDebugEot      = 'h04;
-  localparam byte_bt UartDebugEoc      = 'h14;
-
   logic uart_reading_byte;
 
   initial begin

rtl/test/tb_croc_pkg.sv

@@ -9,9 +9,9 @@
 package tb_croc_pkg;
 
   // Clocks
-  localparam time ClkPeriodSys  = 50ns;    // 20 MHz
-  localparam time ClkPeriodJtag = 50ns;    // 20 MHz
-  localparam time ClkPeriodRef  = 30518ns; // 32 KiHz
+  localparam realtime ClkPeriodSys  = 50ns;    // 20 MHz
+  localparam realtime ClkPeriodJtag = 50ns;    // 20 MHz
+  localparam realtime ClkPeriodRef  = 30518ns; // 32 KiHz
 
   // Number of clock cycles the reset is applied 
   // for at the beginnig of the simulation

rtl/test/tb_croc_soc.sv

@@ -14,12 +14,12 @@ module tb_croc_soc #(
 
   import tb_croc_pkg::*;
 
+  // Signals fully controlled by the VIP
+  // use VIP functions/tasks to manipulate these signals
   logic rst_n;
   logic sys_clk;
   logic ref_clk;
 
-  logic fetch_en;
-
   logic jtag_tck;
   logic jtag_trst_n;
   logic jtag_tms;
@@ -29,17 +29,22 @@ module tb_croc_soc #(
   logic uart_rx;
   logic uart_tx;
 
+  // Signals partially controlled by the VIP
   logic [GpioCount-1:0] gpio_in;
   logic [GpioCount-1:0] gpio_out;
   logic [GpioCount-1:0] gpio_out_en;
 
+  // Signals controlled by the testbench
+  logic fetch_en;
+
   /////////////////////////////
   //  Command Line Arguments //
   /////////////////////////////
 
   string binary_path;
 
   initial begin
+    // $value$plusargs defines what to look for (here +binary=...)
     if ($value$plusargs("binary=%s", binary_path)) begin
       $display("Running program: %s", binary_path);
     end else begin
@@ -51,6 +56,16 @@ module tb_croc_soc #(
   ////////////
   //  VIP   //
   ////////////
+  // Verification IP 
+  // - drives clocks and resets
+  // - provides helper tasks and functions for JTAG, namely:
+  //   - jtag_load_hex: loads a hex file into the DUT's memory
+  //   - jtag_write_reg32: write 32-bit value to DUT
+  //   - jtag_read_reg32: read 32-bit value from DUT
+  //   - jtag_halt / jtag_resume: control core execution
+  //   - jtag_wait_for_eoc: wait for end of code execution (core writes non-zero to status register)
+  // - prints UART output to console (you can also write via uart_write_byte)
+  // - internal GPIO loopback for helloworld test
 
   croc_vip #(
     .GpioCount ( GpioCount )
@@ -108,11 +123,6 @@ module tb_croc_soc #(
 
   initial begin
     $timeformat(-9, 0, "ns", 12); // 1: scale (ns=-9), 2: decimals, 3: suffix, 4: print-field width
-    // configure FST (waveform) dump
-    `ifdef TRACE_WAVE
-    $dumpfile("croc.fst");
-    $dumpvars(1, i_croc_soc);
-    `endif
 
     fetch_en = 1'b0;
 
@@ -142,10 +152,30 @@ module tb_croc_soc #(
 
     // finish simulation
     repeat(50) @(posedge sys_clk);
+    $finish();
+  end
+
+  ////////////////
+  //  Waveform  //
+  ////////////////
+  // start waveform dump at time 0, independent of stimuli
+  initial begin
     `ifdef TRACE_WAVE
-    $dumpflush;
+      `ifdef VERILATOR
+        $dumpfile("croc.fst");
+        $dumpvars(1, i_croc_soc);
+      `else
+        $dumpfile("croc.vcd");
+        $dumpvars(1, i_croc_soc);
+      `endif
+    `endif
+  end
+
+  // flush waveform dump when simulation ends
+  final begin
+    `ifdef TRACE_WAVE
+      $dumpflush;
     `endif
-    $finish();
   end
 
 endmodule

vsim/.gitignore

@@ -5,3 +5,5 @@ transcript
 vsim.wlf
 modelsim.ini
 *.vcd
+*.fst
+*.wlf