hw: replace apb_uart with obi_uart

.github/scripts/check_sim.sh

@@ -12,6 +12,7 @@ expected_lines=(
   "\[JTAG\] Halting hart 0"
   "\[JTAG\] Resumed hart 0"
   "\[UART\] Hello World!"
+  "\[UART\] Loopback received: internal msg"
   "\[UART\] Result: 0x8940, Cycles: 0xBD"
   "\[UART\] Tick"
   "\[UART\] Tock"

Bender.local

@@ -4,7 +4,7 @@ overrides:
   common_cells: { path: "rtl/common_cells" }
   apb: { path: "rtl/apb" }
   register_interface: { path: "rtl/register_interface" }
-  apb_uart: { path: "rtl/apb_uart" }
+  obi_peripherals: { path: "rtl/obi_uart" }
   ibex: { path: "rtl/ibex" }
   obi: { path: "rtl/obi" }
   riscv-dbg: { path: "rtl/riscv-dbg" }

Bender.lock

@@ -6,14 +6,6 @@ packages:
       Path: rtl/apb
     dependencies:
     - common_cells
-  apb_uart:
-    revision: null
-    version: null
-    source:
-      Path: rtl/apb_uart
-    dependencies:
-    - apb
-    - register_interface
   common_cells:
     revision: null
     version: null
@@ -42,6 +34,14 @@ packages:
     dependencies:
     - common_cells
     - common_verification
+  obi_peripherals:
+    revision: null
+    version: null
+    source:
+      Path: rtl/obi_uart
+    dependencies:
+    - common_cells
+    - obi
   register_interface:
     revision: null
     version: null

Bender.yml

@@ -16,8 +16,8 @@ dependencies:
   register_interface:   { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.1  }
   apb:                  { git: "https://github.com/pulp-platform/apb.git",                  version: 0.2.4  }
   timer_unit:           { git: "https://github.com/pulp-platform/timer_unit.git",           version: 1.0.3  }
-  obi:                  { git: "https://github.com/pulp-platform/obi.git",                  version: 0.1.3  }
-  apb_uart:             { git: "https://github.com/pulp-platform/apb_uart.git",             version: 0.2.1  }
+  obi:                  { git: "https://github.com/pulp-platform/obi.git",                  version: 0.1.7  }
+  obi_peripherals:      { git: "https://github.com/pulp-platform/obi_peripherals.git",      rev: 21ee04d    } # UART
   cve2:                 { path: "rtl/cve2" } # a vendor package (no Bender.yml), see below 
 
 
@@ -166,15 +166,13 @@ vendor_package:
       - { from: 'Bender.yml',         to: 'Bender.yml',     patch_dir: '' }
       - { from: 'doc/timer_unit.pdf', to: 'timer_unit.pdf', patch_dir: 'doc/' }
 
-  - name: apb_uart
-    target_dir: rtl/apb_uart
-    upstream: { git: "https://github.com/pulp-platform/apb_uart.git", rev: "6c7dde3d749ac8274377745c105da8c8b8cd27c6"  } # v0.2.1
-    patch_dir: "rtl/patches/apb_uart"
-    exclude_from_upstream:
-      - "src/vhdl_orig"
+  - name: obi_peripherals
+    target_dir: rtl/obi_uart
+    upstream: { git: "https://github.com/pulp-platform/obi_peripherals.git", rev: "21ee04d267025f6ea3d2faa462272287ddcb9bbb"  } # newest
+    patch_dir: "rtl/patches/obi_uart"
     mapping:
-      - { from: 'src/',        to: '',            patch_dir: 'src/' }
-      - { from: 'Bender.yml',  to: 'Bender.yml',  patch_dir: '' }
+      - { from: 'hw/obi_uart/', to: '',            patch_dir: 'hw/' }
+      - { from: 'Bender.yml',   to: 'Bender.yml',  patch_dir: '' }
 
 
   #########

croc.flist

@@ -1,20 +1,3 @@
-# Copyright (c) 2025 ETH Zurich and University of Bologna.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-#
-# Authors:
-# - Philippe Sauter <[email protected]>
-
-# List of files to synthesize the design
-# A file list given to the yosys-slang frontend to load the design
-# In this flow we use 'read_slang -F croc.flist' to load this file
-# All paths are relative to this file (use -f to make them relative to CWD)
-# It contains:
-# - include directores expected from SystemVerilog 'include' statements
-# - defines used in some SystemVerilog files
-#   often used to guard non-synthesisable code or select some implementation
-# - the paths to all source files
-
 +incdir+rtl/apb/include
 +incdir+rtl/common_cells/include
 +incdir+rtl/cve2/include
@@ -108,27 +91,16 @@ rtl/common_cells/stream_arbiter.sv
 rtl/common_cells/stream_omega_net.sv
 rtl/common_cells/mem_to_banks.sv
 rtl/apb/apb_pkg.sv
-rtl/register_interface/reg_intf.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv
-rtl/register_interface/periph_to_reg.sv
-rtl/register_interface/reg_to_apb.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg.sv
-rtl/apb_uart/slib_clock_div.sv
-rtl/apb_uart/slib_counter.sv
-rtl/apb_uart/slib_edge_detect.sv
-rtl/apb_uart/slib_fifo.sv
-rtl/apb_uart/slib_input_filter.sv
-rtl/apb_uart/slib_input_sync.sv
-rtl/apb_uart/slib_mv_filter.sv
-rtl/apb_uart/uart_baudgen.sv
-rtl/apb_uart/uart_interrupt.sv
-rtl/apb_uart/uart_receiver.sv
-rtl/apb_uart/uart_transmitter.sv
-rtl/apb_uart/apb_uart.sv
-rtl/apb_uart/apb_uart_wrap.sv
-rtl/apb_uart/reg_uart_wrap.sv
+rtl/obi/obi_pkg.sv
+rtl/obi/obi_intf.sv
+rtl/obi/obi_rready_converter.sv
+rtl/obi/obi_atop_resolver.sv
+rtl/obi/obi_cut.sv
+rtl/obi/obi_demux.sv
+rtl/obi/obi_err_sbr.sv
+rtl/obi/obi_mux.sv
+rtl/obi/obi_sram_shim.sv
+rtl/obi/obi_xbar.sv
 rtl/cve2/cve2_pkg.sv
 rtl/cve2/cve2_alu.sv
 rtl/cve2/cve2_compressed_decoder.sv
@@ -149,15 +121,21 @@ rtl/cve2/cve2_id_stage.sv
 rtl/cve2/cve2_prefetch_buffer.sv
 rtl/cve2/cve2_if_stage.sv
 rtl/cve2/cve2_core.sv
-rtl/obi/obi_pkg.sv
-rtl/obi/obi_intf.sv
-rtl/obi/obi_rready_converter.sv
-rtl/obi/obi_atop_resolver.sv
-rtl/obi/obi_demux.sv
-rtl/obi/obi_err_sbr.sv
-rtl/obi/obi_mux.sv
-rtl/obi/obi_sram_shim.sv
-rtl/obi/obi_xbar.sv
+rtl/obi_uart/obi_uart_pkg.sv
+rtl/obi_uart/obi_uart_baudgen.sv
+rtl/obi_uart/obi_uart_interrupts.sv
+rtl/obi_uart/obi_uart_modem.sv
+rtl/obi_uart/obi_uart_rx.sv
+rtl/obi_uart/obi_uart_tx.sv
+rtl/obi_uart/obi_uart_register.sv
+rtl/obi_uart/obi_uart.sv
+rtl/register_interface/reg_intf.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv
+rtl/register_interface/periph_to_reg.sv
+rtl/register_interface/reg_to_apb.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg.sv
 rtl/riscv-dbg/dm_pkg.sv
 rtl/riscv-dbg/debug_rom/debug_rom.sv
 rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv