pulp-platform · phsauter · Jul 11, 2025 · Jul 11, 2025 · Jul 11, 2025 · Jul 11, 2025
diff --git a/.cockpitrc b/.cockpitrc
@@ -1,6 +1,6 @@
 [cockpit]
   # Do not change this section
-  config = 2025-1
+  config = 2025-2
 
   # Still Work in Progress
 
@@ -24,6 +24,7 @@
   #                   ixc013g2_iocell_rev1.2.0
   #                   ixc013g2_iocell_rev1.2.1
   #                   open_io_v0.1
+  #                   open_io_v0.2
   #   bondpad       : bondpad_70x70_v0
   #
   #   STD cell      : ixc013g2ng_stdcell_rev0.0.4
@@ -51,15 +52,20 @@
 
   libs    = SG13G2_1.3.1 \
             open_stdcell_v3.2 \
-            open_io_v0.1 \ 
+            open_io_v0.2 \ 
             open_sram_v2.1
 
 
   # send an e-mail to <[email protected]> to ask for macros. Currently available
   # macro datasheets are available under:
   #   /usr/pack/ihp-sg13-kgf/open_ihp_sg13g2/IHP-Open-PDK-main_v2.0/sg13g2_sram
 
-  macros  = RM_IHPSG13_1P_256x64_c2_bm_bist
+  macros  = RM_IHPSG13_1P_1024x64_c2_bm_bist \
+            RM_IHPSG13_1P_2048x64_c2_bm_bist \
+            RM_IHPSG13_1P_256x48_c2_bm_bist \
+            RM_IHPSG13_1P_256x64_c2_bm_bist \
+            RM_IHPSG13_1P_512x64_c2_bm_bist \
+            RM_IHPSG13_1P_64x64_c2_bm_bist
 
 
 [version]
@@ -81,7 +87,7 @@
   innovus   =  innovus-21
   dfii      =  ic-6
   calibre   =  calibre-2021.3
-  oseda     =  oseda -2025.01
+  oseda     =  oseda -2025.07
 
 [command]
   # Startup commands available through the GUI buttons.
@@ -99,8 +105,8 @@
   innovus                      =  xterm -g 136x40 -T innovus-21.13 -e "cds_innovus-21.13.000 innovus"
   calibre                      =  xterm -g 120x40 -T calibredrv-2021.3 -e "./start_calibre 2021.3"
   dfii                         =  ./start_dfii
-  yosys                        =  xterm -g 120x40 -T yosys -e "oseda -2025.01 yosys"
-  openroad                     =  xterm -g 120x40 -T openroad -e "oseda -2025.01 openroad -gui"
-  klayout                      =  xterm -g 120x40 -T klayout -e "setenv KLAYOUT_HOME ./.klayout; oseda -2025.01 klayout -e"
+  yosys                        =  xterm -g 120x40 -T yosys -e "oseda -2025.07 yosys -C"
+  openroad                     =  xterm -g 120x40 -T openroad -e "oseda -2025.07 openroad -gui"
+  klayout                      =  xterm -g 120x40 -T klayout -e "setenv KLAYOUT_HOME ./.klayout; oseda -2025.07 klayout -e"
   dz:llama                     = llama
 
diff --git a/.github/workflows/artistic.yml b/.github/workflows/artistic.yml
@@ -77,7 +77,7 @@ jobs:
       - name: Install packages in OSEDA
         uses: ./.github/actions/oseda-cmd
         with:
-          cmd: "pip install gdspy"
+          cmd: "pip install --break-system-packages gdspy"
       - name: Meercat setup, export top-level GDS
         uses: ./.github/actions/oseda-cmd
         with:

diff --git a/.github/workflows/short-flow.yml b/.github/workflows/short-flow.yml
@@ -35,7 +35,7 @@ jobs:
         uses: actions/upload-artifact@v4
         with:
           name: croc-waveform
-          path: croc.vcd
+          path: croc.fst
         continue-on-error: true
 
       - name: Upload simulation output

diff --git a/Makefile b/Makefile
@@ -88,16 +88,21 @@ vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_chip_yosys_debug.v
 
 
 # Verilator
-VERILATOR_ARGS  = --binary -j 0 -Wno-fatal
-VERILATOR_ARGS += -Wno-style -Wno-WIDTHEXPAND
-VERILATOR_ARGS += --timing --autoflush --trace --trace-structs
+# Turn off style warnings and well-defined SystemVerilog warnings that should be part of -Wno-style
+VERILATOR_ARGS = -Wno-fatal -Wno-style \
+	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
+
+VERILATOR_ARGS += --binary -j 0
+VERILATOR_ARGS += --timing --autoflush --trace-fst --trace-threads 2 --trace-structs
 VERILATOR_ARGS +=  --unroll-count 1 --unroll-stmts 1
+VERILATOR_ARGS += --x-assign fast --x-initial fast
+VERILATOR_CFLAGS += -O3 -march=native -mtune=native
 
 verilator/croc.f: Bender.lock Bender.yml
 	$(BENDER) script verilator -t rtl -t verilator -DSYNTHESIS -DVERILATOR > $@
 
 verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
-	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 -CFLAGS "-O1 -march=native" --top tb_croc_soc -f croc.f
+	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f
 
 ## Simulate RTL using Verilator
 verilator: verilator/obj_dir/Vtb_croc_soc

diff --git a/README.md b/README.md
@@ -39,7 +39,7 @@ The main SoC configurations are in `rtl/croc_pkg.sv`:
 | `BankNumWords`      | `512`            | Number of 32bit words in a memory bank                |
 | `NumSramBanks`      | `2`              | Number of memory banks                                |
 
-The SRAMs are instantiated via a technology wrapper called `tc_sram` (tc: tech_cells), the technology-independent implementation is in `rtl/tech_cells_generic/tc_sram.sv`. A number of SRAM configurations are implemented using IHP130 SRAM memories in `ihp13/tc_sram.sv`. If an unimplemented SRAM configuration is instantiated it will result in a `tc_sram_blackbox` module which can then be easily identified from the synthesis results.
+The SRAMs are instantiated via a technology wrapper called `tc_sram_impl` (tc: tech_cells), the technology-independent implementation is in `rtl/tech_cells_generic/tc_sram_impl.sv`. A number of SRAM configurations are implemented using IHP130 SRAM memories in `ihp13/tc_sram_impl.sv`. If an unimplemented SRAM configuration is instantiated it will result in a `tc_sram_blackbox` module which can then be easily identified from the synthesis results.
 
 ## Bootmodes
 

diff --git a/docker-compose.yml b/docker-compose.yml
@@ -7,7 +7,7 @@
 
 services:
   pulp-docker:
-    image: hpretl/iic-osic-tools:2025.03
+    image: hpretl/iic-osic-tools:2025.07.pre1
     environment:
       - UID=${UID}
       - GID=${GID}

diff --git a/ethz.env b/ethz.env
@@ -7,9 +7,9 @@
 # - Philippe Sauter <[email protected]>
 
 # used in Makefiles
-export BENDER="oseda bender"
-export OPENROAD="oseda openroad"
-export KLAYOUT="oseda klayout"
-export YOSYS="oseda yosys"
-export PYTHON3="oseda python3"
-export VERILATOR="oseda verilator"
+export BENDER="oseda -2025.07 bender"
+export OPENROAD="oseda -2025.07 openroad"
+export KLAYOUT="oseda -2025.07 klayout"
+export YOSYS="oseda -2025.07 yosys"
+export PYTHON3="oseda -2025.07 python3"
+export VERILATOR="oseda -2025.07 verilator"
diff --git a/klayout/def2gds.sh b/klayout/def2gds.sh
@@ -11,14 +11,23 @@ cd $klayout_dir
 ################
 ### project  ###
 ################
-topcell="croc_chip"
-defpath="$root_dir/openroad/out/croc.def"
+top_design=${TOP_DESIGN:-"croc_chip"}
+def_path=${DEF_PATH:-"$root_dir/openroad/out/croc.def"}
 
 
 ################
 ## technology ##
 ################
-if [[ -f "$root_dir/cockpit.log" ]]; then
+tech="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt"
+layer="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp"
+
+# create klayout home dir and add pdk to path
+export KLAYOUT_HOME="$klayout_dir/.klayout"
+export KLAYOUT_PATH="$(realpath $root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout):$KLAYOUT_PATH"
+mkdir -p $KLAYOUT_HOME/tech
+
+
+if [[ -d "$root_dir/technology" ]]; then
     echo "Init tech from ETHZ DZ cockpit"
     pdk_dir=$(realpath "$root_dir/technology")
     pdk_cells_lef_dir="${pdk_dir}/lef"
@@ -52,13 +61,8 @@ gds="$(find "$pdk_cells_gds_dir" -name 'sg13g2_stdcell.gds' -exec realpath {} \;
      $(find "$pdk_io_gds_dir" -name 'sg13g2_io.gds' -exec realpath {} \;) \
      $(find "$bondpad_gds_dir" -name '*.gds' -exec realpath {} \;)"
 
-tech="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt"
-layer="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp"
 
-# create klayout home dir and add pdk to path
-export KLAYOUT_HOME="$klayout_dir/.klayout"
-export KLAYOUT_PATH="$(realpath $root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout):$KLAYOUT_PATH"
-mkdir -p $KLAYOUT_HOME/tech
+ln -sfr $klayout_dir/sg13g2.map $KLAYOUT_HOME/tech/sg13g2.map
 
 # all <lef-files> entries for the tech file
 lef_files=""
@@ -68,15 +72,15 @@ done
 
 # replace the placeholder tag with the real lef files
 sed "/<lef-files><\/lef-files>/c $lef_files" "$tech" > $KLAYOUT_HOME/tech/sg13g2.lyt
-ln -sfr $klayout_dir/sg13g2.map $KLAYOUT_HOME/tech/sg13g2.map
 
 echo "$gds" > $KLAYOUT_HOME/tech/tech_gds.f
 
+
 klayout_cmd="$KLAYOUT -zz \
-          -rd design_name=\"$topcell\" \
-          -rd in_def=\"$defpath\" \
+          -rd design_name=\"$top_design\" \
+          -rd in_def=\"$def_path\" \
           -rd gds_flist=\"$KLAYOUT_HOME/tech/tech_gds.f\" \
-          -rd out_file=\"${topcell}.gds\" \
+          -rd out_file=\"${top_design}.gds\" \
           -rd tech_file=\"$KLAYOUT_HOME/tech/sg13g2.lyt\" \
           -rd layer_map=\"$KLAYOUT_HOME/tech/sg13g2.map\" \
           -rm def2stream.py"

diff --git a/openroad/scripts/chip.tcl b/openroad/scripts/chip.tcl
@@ -25,6 +25,7 @@ source scripts/init_tech.tcl
 
 set log_id 0
 
+
 ###############################################################################
 # Initialization                                                              #
 ###############################################################################
@@ -291,6 +292,7 @@ report_metrics "${log_id_str}_${proj_name}.grt_repaired"
 save_checkpoint ${log_id_str}_${proj_name}.grt_repaired
 report_image "${log_id_str}_${proj_name}.grt_repaired" true true false true
 
+
 ###############################################################################
 # DETAILED ROUTE                                                              #
 ###############################################################################
@@ -320,6 +322,7 @@ save_checkpoint ${log_id_str}_${proj_name}.drt
 report_metrics "${log_id_str}_${proj_name}.drt"
 report_image "${log_id_str}_${proj_name}.drt" true false false true
 
+
 ###############################################################################
 # FINISHING                                                                   #
 ###############################################################################
@@ -335,10 +338,7 @@ global_connect
 
 save_checkpoint ${log_id_str}_${proj_name}.final
 report_image "${log_id_str}_${proj_name}.final" true true false true
-define_process_corner -ext_model_index 0 X
-extract_parasitics -ext_model_file IHP_rcx_patterns.rules
-write_spef out/${proj_name}.spef
-read_spef  out/${proj_name}.spef; # readback parasitics for OpenSTA
+estimate_parasitics -global_routing
 report_metrics "${log_id_str}_${proj_name}.final"
 
 utl::report "Write output"
@@ -348,4 +348,12 @@ write_verilog                  out/${proj_name}.v
 write_db                       out/${proj_name}.odb
 write_sdc                      out/${proj_name}.sdc
 
+## WARNING: Currently the extract_parasitics command removes metal patches (eg for min area)
+## So if you want to use it, do so at the very end after writing out the def and odb files
+# define_process_corner -ext_model_index 0 X
+# extract_parasitics -ext_model_file IHP_rcx_patterns.rules
+# write_spef out/${proj_name}.spef
+# read_spef  out/${proj_name}.spef; # readback parasitics for OpenSTA
+# report_metrics "${log_id_str}_${proj_name}.extract"
+
 exit
diff --git a/openroad/scripts/init_tech.tcl b/openroad/scripts/init_tech.tcl
@@ -9,7 +9,7 @@
 
 # Initialize the PDK
 
-if {[file exists "../cockpit.log"]} {
+if {[file exists "../technology"]} {
 	utl::report "Init tech from ETHZ DZ cockpit"
 	set pdk_dir "../technology"
 	set pdk_cells_lib ${pdk_dir}/lib

diff --git a/rtl/tb_croc_soc.sv b/rtl/tb_croc_soc.sv
@@ -441,9 +441,9 @@ module tb_croc_soc #(
 
     initial begin
         $timeformat(-9, 0, "ns", 12); // 1: scale (ns=-9), 2: decimals, 3: suffix, 4: print-field width
-        // configure VCD dump
+        // configure FST (waveform) dump
         `ifdef TRACE_WAVE
-        $dumpfile("croc.vcd");
+        $dumpfile("croc.fst");
         $dumpvars(1,i_croc_soc);
         `endif
 

diff --git a/start_vnc.bat b/start_vnc.bat
@@ -46,7 +46,7 @@ if not exist "%DESIGNS%" %ECHO_IF_DRY_RUN% mkdir "%DESIGNS%"
 
 IF "%DOCKER_USER%"=="" SET DOCKER_USER=hpretl
 IF "%DOCKER_IMAGE%"=="" SET DOCKER_IMAGE=iic-osic-tools
-IF "%DOCKER_TAG%"=="" SET DOCKER_TAG=2025.03
+IF "%DOCKER_TAG%"=="" SET DOCKER_TAG=2025.07.pre1
 
 IF "%CONTAINER_USER%"=="" SET CONTAINER_USER=1000
 IF "%CONTAINER_GROUP%"=="" SET CONTAINER_GROUP=1000

diff --git a/start_vnc.sh b/start_vnc.sh
@@ -52,7 +52,7 @@ if [ -z ${DOCKER_IMAGE+z} ]; then
 fi
 
 if [ -z ${DOCKER_TAG+z} ]; then
-	DOCKER_TAG="2025.03"
+	DOCKER_TAG="2025.07.pre1"
 fi
 
 if [ -z ${CONTAINER_NAME+z} ]; then

diff --git a/vsim/compile_tech.tcl b/vsim/compile_tech.tcl
@@ -17,5 +17,5 @@ if {[catch { vlog -incr -sv \
     "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \
     "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \
     "$ROOT/ihp13/tc_sram.sv" \
-    "$ROOT/ihp13/tc_clk.sv" \
-}]} {return 1}
+    "$ROOT/ihp13/tc_clk.s_implv" \
+}]} {return 1}