RISC-V: Set insn info fields correctly when disassembling. #2
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RISC-V: Set insn info fields correctly when disassembling. #2
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This fixes a problem reported via github
riscvarchive/riscv-binutils-gdb#153
We are setting insn_info_valid, but not setting insn_type and data_size. This
patch adds support to set the two fields.
This was tested by adding some code to print the two fields, disassembling
libstdc++, and then checking to make sure the output was right. It was also
testing with cross riscv{32,64}-{elf,linux} builds and make checks, and there
were no regressions.
Committed.
Jim
The original patch is from
https://sourceware.org/ml/binutils/2018-07/msg00508.html and is ported
to PULP binutils (which is about version 1.28) by me. Use git diff
--word-diff for a better overview of the changes.
Robert
include/
* opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
(INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
(INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
fields.
* riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
gtagliavini
added a commit
that referenced
this pull request
Apr 14, 2020
extend binutils to support SPR 2 and 3 (mac&load)
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I ported this patch from binutils 1.30. The disassembler struct (
disassembler_info) has a member struct (insn_type) that should be filled out with the appropriate information for the currently disassembled instruction. This was handled not at all before, despite signaling that information was filled in.This patch is basically only relevant if one uses the opcodes library.