HWPE integration

Bender.yml

@@ -13,39 +13,34 @@ package:
     - "Luca Valente <[email protected]>"
 
 dependencies:
-  L2_tcdm_hybrid_interco: { git: "https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git", version: 1.0.0 }
   apb:                    { git: "https://github.com/pulp-platform/apb.git", version:  0.2.2 }
   adv_dbg_if:             { git: "https://github.com/pulp-platform/adv_dbg_if.git", version: 0.0.2 }
   apb2per:                { git: "https://github.com/pulp-platform/apb2per.git", version: 0.1.0 }
   apb_adv_timer:          { git: "https://github.com/pulp-platform/apb_adv_timer.git", version: 1.0.4 }
   apb_fll_if:             { git: "https://github.com/pulp-platform/apb_fll_if.git", version: 0.2.0 }
   apb_interrupt_cntrl:    { git: "https://github.com/pulp-platform/apb_interrupt_cntrl.git", version: 0.2.0 }
-  axi:                    { git: "https://github.com/pulp-platform/axi.git", version: 0.38.0 }
-  # axi_node:               { git: "https://github.com/pulp-platform/axi_node.git", version: 1.1.4 } # deprecated, replaced by axi_xbar (in axi repo)
-  axi_slice:              { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo)
+  axi:                    { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 }
   timer_unit:             { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
   common_cells:           { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 }
   cluster_interconnect:   { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.1.1 }
-  fpnew:                  { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.6 }
+  fpnew:                  { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.3 }
   jtag_pulp:              { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 }
-  cv32e40p:               { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "pulpissimo-v4.1.0"}
+  cv32e40p:               { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "7a49867b2232d97344cde1b8a1e05bcb38634894"}
   ibex:                   { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" }
   scm:                    { git: "https://github.com/pulp-platform/scm.git", version: 1.0.1}
   generic_FLL:            { git: "https://github.com/pulp-platform/generic_FLL.git", version: 0.2.0 }
   tech_cells_generic:     { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
   pulp_io:                { git: "https://github.com/pulp-platform/pulp-io.git", rev: v0.1.0-draft }
-  hwpe-mac-engine:        { git: "https://github.com/pulp-platform/hwpe-mac-engine.git", version: 1.3.3 }
+  fir-hwpe:               { git: "[email protected]:ades-labs/fir-hwpe.git", rev: "cb6b9a5f9dd0c01dabb77af827f293f1427d4f03" }
   riscv-dbg:              { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.5.0 }
-  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 }
+  register_interface:     { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 }
 
 sources:
   # pulp_soc
   - include_dirs:
       - rtl/include
     files:
       - rtl/pulp_soc/pkg_soc_interconnect.sv
-      - rtl/pulp_soc/axi64_2_lint32_wrap.sv
-      - rtl/pulp_soc/lint_2_axi_wrap.sv
       - rtl/pulp_soc/contiguous_crossbar.sv
       - rtl/pulp_soc/interleaved_crossbar.sv
       - rtl/pulp_soc/tcdm_demux.sv

CHANGELOG.md

@@ -5,6 +5,13 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ## [Unreleased]
+- Use pulp-io for peripherals -> updated udma subsystem and corresponding peripherals
+- Use new gpio peripheral
+- Externalize clock generator modules
+- Remove IPApproX support
+- Clean up & update dependencies
+- Update AXI to TCDM IPs
+
 ## [4.4.0] - 2022-06-10
 - Bump cv32e40p to pulpissimo-v4.1.0 (Unlock all interrupts and increases fpu latency)
 

Makefile

@@ -4,6 +4,7 @@ VENVDIR?=$(WORKDIR)/.venv
 REQUIREMENTS_TXT?=$(wildcard requirements.txt)
 include Makefile.venv
 
+.PHONY: regenerate_soc_ctrl
 ## Regenerate the register file and HAL C-header the soc_ctrl register.
 regenerate_soc_ctrl: | venv
 	@echo Regenerating SoC control register...

rtl/components/tcdm_arbiter_2x1.sv

@@ -1,18 +1,14 @@
-/*
- * Copyright (C) 2013-2017 ETH Zurich, University of Bologna
- * All rights reserved.
- *
- * This code is under development and not yet released to the public.
- * Until it is released, the code is under the copyright of ETH Zurich and
- * the University of Bologna, and may contain confidential and/or unpublished
- * work. Any reuse/redistribution is strictly forbidden without written
- * permission from ETH Zurich.
- *
- * Bug fixes and contributions will eventually be released under the
- * SolderPad open hardware license in the context of the PULP platform
- * (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
- * University of Bologna.
- */
+// Copyright 2013-2024 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// mux two tcdm ports to one
 
 module tcdm_arbiter_2x1
 (

rtl/fc/cv32e40p_fp_wrapper.sv

@@ -64,21 +64,23 @@ localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
   Width:         C_FLEN,
   EnableVectors: C_XFVEC,
   EnableNanBox:  1'b0,
-  FpFmtMask:     {C_RVF, C_RVD, C_XF16, C_XF8, C_XF16ALT},
-  IntFmtMask:    {C_XFVEC && C_XF8, C_XFVEC && (C_XF16 || C_XF16ALT), 1'b1, 1'b0}
+  FpFmtMask:     {C_RVF, C_RVD, C_XF16, C_XF8, C_XF16ALT, C_XF8ALT},
+  IntFmtMask:    {C_XFVEC && (C_XF8 || C_XF8ALT), C_XFVEC && (C_XF16 || C_XF16ALT), 1'b1, 1'b0}
 };
 
 // Implementation (number of registers etc)
 localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
   PipeRegs:  '{// FP32, FP64, FP16, FP8, FP16alt
-               '{C_LAT_FP32, C_LAT_FP64, C_LAT_FP16, C_LAT_FP8, C_LAT_FP16ALT}, // ADDMUL
+               '{C_LAT_FP32, C_LAT_FP64, C_LAT_FP16, C_LAT_FP8, C_LAT_FP16ALT, C_LAT_FP8ALT}, // ADDMUL
                '{default: C_LAT_DIVSQRT}, // DIVSQRT
                '{default: C_LAT_NONCOMP}, // NONCOMP
-               '{default: C_LAT_CONV}},   // CONV
+               '{default: C_LAT_CONV},    // CONV
+               '{default: C_LAT_DOTP}},   // DOTP
   UnitTypes: '{'{default: fpnew_pkg::MERGED},   // ADDMUL
                '{default: C_DIV},   // DIVSQRT
                '{default: fpnew_pkg::PARALLEL}, // NONCOMP
-               '{default: fpnew_pkg::MERGED}},  // CONV
+               '{default: fpnew_pkg::MERGED},   // CONV
+               '{default: fpnew_pkg::DISABLED}}, // DOTP
   PipeConfig: fpnew_pkg::AFTER
 };
 
@@ -89,10 +91,16 @@ localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
 fpnew_top #(
   .Features       ( FPU_FEATURES       ),
   .Implementation ( FPU_IMPLEMENTATION ),
-  .TagType        ( logic              )
+  .TagType        ( logic              ),
+  .PulpDivsqrt    ( 1'b0               ),
+  .TrueSIMDClass  ( 1'b0               ),
+  .EnableSIMDMask ( 1'b0               ),
+  .CompressedVecCmpResult ( 1'b0       ),
+  .StochasticRndImplementation ( fpnew_pkg::DEFAULT_NO_RSR )
 ) i_fpnew_bulk (
   .clk_i          ( clk_i                                 ),
   .rst_ni         ( rst_ni                                ),
+  .hart_id_i      ( '0                                    ),
   .operands_i     ( apu_operands_i                        ),
   .rnd_mode_i     ( fpnew_pkg::roundmode_e'(fp_rnd_mode)  ),
   .op_i           ( fpnew_pkg::operation_e'(fpu_op)       ),
@@ -102,6 +110,7 @@ fpnew_top #(
   .int_fmt_i      ( fpnew_pkg::int_format_e'(fpu_int_fmt) ),
   .vectorial_op_i ( fpu_vec_op                            ),
   .tag_i          ( 1'b0                                  ),
+  .simd_mask_i    ( '1                                    ),
   .in_valid_i     ( apu_req_i                             ),
   .in_ready_o     ( apu_gnt_o                             ),
   .flush_i        ( 1'b0                                  ),

rtl/fc/fc_hwpe.sv

@@ -74,9 +74,9 @@ module fc_hwpe
         .per_master_r_rdata_i ( periph_r_rdata          )
     );
 
-    mac_top_wrap #(
+    fir_top_wrap #(
         .ID  ( ID_WIDTH )
-    ) i_mac_top_wrap (
+    ) i_fir_top_wrap (
         .clk_i            ( clk_i          ),
         .rst_ni           ( rst_ni         ),
         .test_mode_i      ( test_mode_i    ),

rtl/pulp_soc/boot_rom.sv

@@ -40,34 +40,27 @@ module boot_rom #(
 
     `ifndef PULP_FPGA_EMUL
 
-        generic_rom #(
-            .ADDR_WIDTH(ROM_ADDR_WIDTH-2), //The ROM uses 32-bit word addressing while the bus addresses bytes
-            .DATA_WIDTH(32),
-            .FILE_NAME("./boot/boot_code.cde") // CDE file is looked for in a
-                                              // folder relative to the
-                                              // simulation folder.
-         ) rom_mem_i (
-            .CLK            (  clk_i                ),
-            .CEN            (  ~mem_slave.req        ),
-            .A              (  address[ROM_ADDR_WIDTH-1:2]  ), //Cutoff insignificant address bits. The
-                                                                     //interconnect makes sure we only receive addresses in the bootrom address space
-            .Q              (  mem_slave.r_rdata      )
+        asic_autogen_rom #(
+            .ADDR_WIDTH(ROM_ADDR_WIDTH-2),
+            .DATA_WIDTH(32)
+        ) rom_mem_i (
+            .CLK ( clk_i                       ),
+            .CEN ( ~mem_slave.req              ),
+            .A   ( address[ROM_ADDR_WIDTH-1:2] ),
+            .Q   ( mem_slave.r_rdata           )
         );
 
-        // assign mem_slave.add[31:ROM_ADDR_WIDTH] = '0;
-
     `else // !`ifndef PULP_FPGA_EMUL
 
-    fpga_bootrom #(
-                   .ADDR_WIDTH(ROM_ADDR_WIDTH-2), //The ROM uses 32-bit word addressing while the bus addresses bytes
-                   .DATA_WIDTH(32)
-                   ) rom_mem_i (
-                            .CLK(clk_i),
-                            .CEN(~mem_slave.req),
-                            .A(address[ROM_ADDR_WIDTH-1:2]), //Cutoff insignificant address bits. The interconnect
-                                                                   //makes sure we only receive addresses in the bootrom address space
-                            .Q(mem_slave.r_rdata)
-                            );
+        fpga_autogen_rom #(
+            .ADDR_WIDTH(ROM_ADDR_WIDTH-2),
+            .DATA_WIDTH(32)
+        ) rom_mem_i (
+            .CLK ( clk_i                       ),
+            .CEN ( ~mem_slave.req              ),
+            .A   ( address[ROM_ADDR_WIDTH-1:2] ),
+            .Q   ( mem_slave.r_rdata           )
+        );
 
     `endif