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Andrea Belano
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[xif] Make custom opcode and funct fields parametric
1 parent 08c2ac2 commit ba7b93d

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2 files changed

+29
-11
lines changed

2 files changed

+29
-11
lines changed

‎rtl/redmule_inst_decoder.sv‎

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,12 @@
88
module redmule_inst_decoder
99
import redmule_pkg::*;
1010
#(
11+
parameter logic [6:0] McnfigOpCode = 7'b0001011,
12+
parameter logic [6:0] MarithOpCode = 7'b0001011,
13+
parameter logic [2:0] McnfigFunct3 = 3'b000,
14+
parameter logic [2:0] MarithFunct3 = 3'b001,
15+
parameter logic [1:0] McnfigFunct2 = 2'b00,
16+
parameter logic [1:0] MarithFunct2 = 2'b00,
1117
parameter int unsigned InstFifoDepth = 4,
1218
parameter int unsigned OpIdWidth = 4,
1319
parameter int unsigned XifIdWidth = 4,
@@ -23,7 +29,6 @@ module redmule_inst_decoder
2329
input logic rst_ni,
2430
input logic clear_i,
2531
input logic config_ready_i,
26-
input logic tiler_done_i,
2732
input logic op_done_i,
2833
output logic config_valid_o,
2934
output redmule_config_t config_o,
@@ -43,6 +48,9 @@ module redmule_inst_decoder
4348

4449
localparam int unsigned HartIdWidth = XifNumHarts > 1 ? $clog2(XifNumHarts) : 1;
4550

51+
localparam logic [11:0] MCNFIG = {McnfigFunct2,McnfigFunct3,McnfigOpCode};
52+
localparam logic [11:0] MARITH = {MarithFunct2,MarithFunct3,MarithOpCode};
53+
4654
logic [XifNumHarts-1:0] issue_fifo_full, register_fifo_full,
4755
issue_fifo_empty, register_fifo_empty;
4856
logic [HartIdWidth-1:0] current_hartid_d, current_hartid_q;
@@ -67,25 +75,25 @@ module redmule_inst_decoder
6775
always_comb begin : legal_inst_assignment
6876
legal_inst = 1'b0;
6977

70-
unique case (x_issue_req_i.instr[6:0])
78+
unique case ({x_issue_req_i.instr[26:25],x_issue_req_i.instr[14:12],x_issue_req_i.instr[6:0]})
7179
MCNFIG, MARITH: legal_inst = 1'b1;
7280
default: legal_inst = 1'b0;
7381
endcase
7482
end
7583

7684
assign x_issue_resp_o.accept = legal_inst;
77-
assign x_issue_resp_o.writeback = x_issue_req_i.instr[6:0] == MARITH;
85+
assign x_issue_resp_o.writeback = {x_issue_req_i.instr[26:25],x_issue_req_i.instr[14:12],x_issue_req_i.instr[6:0]} == MARITH && x_issue_req_i.instr[11:7] != 0;
7886
assign x_issue_resp_o.register_read = 7; // We always read 3 registers
7987

8088
assign x_result_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner];
8189
assign x_result_o.hartid = cur_issue[winner].hartid;
8290
assign x_result_o.id = cur_issue[winner].id;
8391
assign x_result_o.data = op_id_counter_in_q[winner];
8492
assign x_result_o.rd = cur_issue[winner].instr[11:7];
85-
assign x_result_o.we = cur_issue[winner].instr[6:0] == MARITH;
93+
assign x_result_o.we = {cur_issue[winner].instr[26:25],cur_issue[winner].instr[14:12],cur_issue[winner].instr[6:0]} == MARITH && cur_issue[winner].instr[11:7] != 0;
8694

8795
assign config_o = config_d[winner];
88-
assign config_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner] && x_result_ready_i && cur_issue[winner].instr[6:0] == MARITH;
96+
assign config_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner] && x_result_ready_i && {cur_issue[winner].instr[26:25],cur_issue[winner].instr[14:12],cur_issue[winner].instr[6:0]} == MARITH;
8997

9098
always_comb begin : x_issue_ready_assignment
9199
x_issue_ready_o = 1'b0;
@@ -162,7 +170,7 @@ module redmule_inst_decoder
162170
end else begin
163171
if (clear_i) begin
164172
op_id_counter_in_q[i] <= 0;
165-
end else if (winner == i && x_result_ready_i && x_result_valid_o && cur_issue[i].instr[6:0] == MARITH) begin
173+
end else if (winner == i && x_result_ready_i && x_result_valid_o && {cur_issue[i].instr[26:25],cur_issue[i].instr[14:12],cur_issue[i].instr[6:0]} == MARITH) begin
166174
op_id_counter_in_q[i] <= op_id_counter_in_q[i] + 1;
167175
end
168176
end
@@ -182,11 +190,9 @@ module redmule_inst_decoder
182190
end
183191

184192
// Pop the fifos the first cycle the tiler is no longer busy if we detect a MARITH instruction
185-
assign pop_enable = (cur_issue[winner].instr[6:0] == MARITH ? config_ready_i && config_valid_o : 1'b1);
193+
assign pop_enable = ({cur_issue[winner].instr[26:25],cur_issue[winner].instr[14:12],cur_issue[winner].instr[6:0]} == MARITH ? config_ready_i && config_valid_o : 1'b1);
186194

187195
for (genvar i = 0; i < XifNumHarts; i++) begin : gen_instruction_fifos
188-
189-
190196
logic [XifIdWidth-1:0] commit_id_d, commit_id_q,
191197
kill_id_d, kill_id_q;
192198

@@ -327,7 +333,7 @@ module redmule_inst_decoder
327333
always_comb begin : config_assignment
328334
config_d[i] = config_q[i];
329335

330-
unique case (cur_issue[i].instr[6:0])
336+
unique case ({cur_issue[i].instr[26:25],cur_issue[i].instr[14:12],cur_issue[i].instr[6:0]})
331337
MCNFIG: begin
332338
config_d[i].m_size = cur_register[i].rs[0][15:0];
333339
config_d[i].n_size = cur_register[i].rs[1][15:0];

‎rtl/redmule_top.sv‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,13 @@ module redmule_top
2727
parameter int unsigned NumPipeRegs = PIPE_REGS , // Number of pipeline registers within each PE
2828
parameter pipe_config_t PipeConfig = DISTRIBUTED ,
2929
parameter int unsigned BITW = fp_width(FpFormat), // Number of bits for the given format
30+
// Custom instrunctions
31+
parameter logic [6:0] McnfigOpCode = 7'b0001011,
32+
parameter logic [6:0] MarithOpCode = 7'b0001011,
33+
parameter logic [2:0] McnfigFunct3 = 3'b000,
34+
parameter logic [2:0] MarithFunct3 = 3'b001,
35+
parameter logic [1:0] McnfigFunct2 = 2'b00,
36+
parameter logic [1:0] MarithFunct2 = 2'b00,
3037
// XIF parameters
3138
parameter int unsigned XifNumHarts = 1,
3239
parameter int unsigned XifIdWidth = 1,
@@ -572,6 +579,12 @@ redmule_config_t dec_config_q;
572579

573580
redmule_inst_decoder #(
574581
.InstFifoDepth ( 4 ),
582+
.McnfigOpCode ( McnfigOpCode ),
583+
.MarithOpCode ( MarithOpCode ),
584+
.McnfigFunct3 ( McnfigFunct3 ),
585+
.MarithFunct3 ( MarithFunct3 ),
586+
.McnfigFunct2 ( McnfigFunct2 ),
587+
.MarithFunct2 ( MarithFunct2 ),
575588
.XifIdWidth ( XifIdWidth ),
576589
.XifNumHarts ( XifNumHarts ),
577590
.XifIssueRegisterSplit ( XifIssueRegisterSplit ),
@@ -585,7 +598,6 @@ redmule_inst_decoder #(
585598
.rst_ni ( rst_ni ),
586599
.clear_i ( '0 ),
587600
.config_ready_i ( ~config_fifo_full ),
588-
.tiler_done_i ( /*cfg_complete*/ ),
589601
.op_done_i ( flgs_streamer.z_stream_sink_flags.done ),
590602
.config_valid_o ( dec_config_valid ),
591603
.config_o ( dec_config ),

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