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Commit d8d9c70

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author
Andrea Belano
committed
[xif] Add MOPCNT instruction
1 parent ba7b93d commit d8d9c70

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2 files changed

+65
-15
lines changed

2 files changed

+65
-15
lines changed

‎rtl/redmule_inst_decoder.sv‎

Lines changed: 54 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,13 @@ module redmule_inst_decoder
1010
#(
1111
parameter logic [6:0] McnfigOpCode = 7'b0001011,
1212
parameter logic [6:0] MarithOpCode = 7'b0001011,
13+
parameter logic [6:0] MopcntOpCode = 7'b0001011,
1314
parameter logic [2:0] McnfigFunct3 = 3'b000,
1415
parameter logic [2:0] MarithFunct3 = 3'b001,
16+
parameter logic [2:0] MopcntFunct3 = 3'b010,
1517
parameter logic [1:0] McnfigFunct2 = 2'b00,
1618
parameter logic [1:0] MarithFunct2 = 2'b00,
19+
parameter logic [1:0] MopcntFunct2 = 2'b00,
1720
parameter int unsigned InstFifoDepth = 4,
1821
parameter int unsigned OpIdWidth = 4,
1922
parameter int unsigned XifIdWidth = 4,
@@ -50,6 +53,7 @@ module redmule_inst_decoder
5053

5154
localparam logic [11:0] MCNFIG = {McnfigFunct2,McnfigFunct3,McnfigOpCode};
5255
localparam logic [11:0] MARITH = {MarithFunct2,MarithFunct3,MarithOpCode};
56+
localparam logic [11:0] MOPCNT = {MopcntFunct2,MopcntFunct3,MopcntOpCode};
5357

5458
logic [XifNumHarts-1:0] issue_fifo_full, register_fifo_full,
5559
issue_fifo_empty, register_fifo_empty;
@@ -76,21 +80,60 @@ module redmule_inst_decoder
7680
legal_inst = 1'b0;
7781

7882
unique case ({x_issue_req_i.instr[26:25],x_issue_req_i.instr[14:12],x_issue_req_i.instr[6:0]})
79-
MCNFIG, MARITH: legal_inst = 1'b1;
83+
MCNFIG, MARITH, MOPCNT: legal_inst = 1'b1;
8084
default: legal_inst = 1'b0;
8185
endcase
8286
end
8387

84-
assign x_issue_resp_o.accept = legal_inst;
85-
assign x_issue_resp_o.writeback = {x_issue_req_i.instr[26:25],x_issue_req_i.instr[14:12],x_issue_req_i.instr[6:0]} == MARITH && x_issue_req_i.instr[11:7] != 0;
86-
assign x_issue_resp_o.register_read = 7; // We always read 3 registers
88+
always_comb begin : x_issue_resp_assignment
89+
x_issue_resp_o.accept = legal_inst;
8790

88-
assign x_result_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner];
89-
assign x_result_o.hartid = cur_issue[winner].hartid;
90-
assign x_result_o.id = cur_issue[winner].id;
91-
assign x_result_o.data = op_id_counter_in_q[winner];
92-
assign x_result_o.rd = cur_issue[winner].instr[11:7];
93-
assign x_result_o.we = {cur_issue[winner].instr[26:25],cur_issue[winner].instr[14:12],cur_issue[winner].instr[6:0]} == MARITH && cur_issue[winner].instr[11:7] != 0;
91+
unique case ({x_issue_req_i.instr[26:25],x_issue_req_i.instr[14:12],x_issue_req_i.instr[6:0]})
92+
MCNFIG: begin
93+
x_issue_resp_o.writeback = 'b0;
94+
x_issue_resp_o.register_read = 'b011;
95+
end
96+
MARITH: begin
97+
x_issue_resp_o.writeback = x_issue_req_i.instr[11:7] != 0;
98+
x_issue_resp_o.register_read = 'b111;
99+
end
100+
MOPCNT: begin
101+
x_issue_resp_o.writeback = x_issue_req_i.instr[11:7] != 0;
102+
x_issue_resp_o.register_read = 'b0;
103+
end
104+
default: begin
105+
x_issue_resp_o.writeback = 'b0;
106+
x_issue_resp_o.register_read = 'b0;
107+
end
108+
endcase
109+
end
110+
111+
112+
always_comb begin : x_result_assignment
113+
x_result_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner];
114+
x_result_o.hartid = cur_issue[winner].hartid;
115+
x_result_o.id = cur_issue[winner].id;
116+
x_result_o.rd = cur_issue[winner].instr[11:7];
117+
118+
unique case ({cur_issue[winner].instr[26:25],cur_issue[winner].instr[14:12],cur_issue[winner].instr[6:0]})
119+
MCNFIG: begin
120+
x_result_o.we = 'b0;
121+
x_result_o.data = 'b0;
122+
end
123+
MARITH: begin
124+
x_result_o.we = cur_issue[winner].instr[11:7] != 0;
125+
x_result_o.data = op_id_counter_in_q[winner];
126+
end
127+
MOPCNT: begin
128+
x_result_o.we = cur_issue[winner].instr[11:7] != 0;
129+
x_result_o.data = op_id_counter_out_q[winner];
130+
end
131+
default: begin
132+
x_result_o.we = 'b0;
133+
x_result_o.data = 'b0;
134+
end
135+
endcase
136+
end
94137

95138
assign config_o = config_d[winner];
96139
assign config_valid_o = ~issue_fifo_empty[winner] && ~register_fifo_empty[winner] && x_result_ready_i && {cur_issue[winner].instr[26:25],cur_issue[winner].instr[14:12],cur_issue[winner].instr[6:0]} == MARITH;
@@ -352,6 +395,7 @@ module redmule_inst_decoder
352395
config_d[i].gemm_input_fmt = redmule_pkg::Float16;
353396
config_d[i].gemm_output_fmt = redmule_pkg::Float16;
354397
end
398+
default: config_d[i] = config_q[i];
355399
endcase
356400
end
357401
end

‎rtl/redmule_top.sv‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,13 @@ module redmule_top
3030
// Custom instrunctions
3131
parameter logic [6:0] McnfigOpCode = 7'b0001011,
3232
parameter logic [6:0] MarithOpCode = 7'b0001011,
33+
parameter logic [6:0] MopcntOpCode = 7'b0001011,
3334
parameter logic [2:0] McnfigFunct3 = 3'b000,
3435
parameter logic [2:0] MarithFunct3 = 3'b001,
36+
parameter logic [2:0] MopcntFunct3 = 3'b010,
3537
parameter logic [1:0] McnfigFunct2 = 2'b00,
3638
parameter logic [1:0] MarithFunct2 = 2'b00,
39+
parameter logic [1:0] MopcntFunct2 = 2'b00,
3740
// XIF parameters
3841
parameter int unsigned XifNumHarts = 1,
3942
parameter int unsigned XifIdWidth = 1,
@@ -135,10 +138,10 @@ logic dec_config_valid;
135138
logic config_fifo_empty, config_fifo_full;
136139

137140
tc_clk_gating i_acc_clock_gating (
138-
.clk_i ( clk_i ),
139-
.en_i ( dec_config_valid | config_fifo_empty | busy_o ),
140-
.test_en_i ( '0 ),
141-
.clk_o ( clk_acc )
141+
.clk_i ( clk_i ),
142+
.en_i ( dec_config_valid | ~config_fifo_empty | busy_o ),
143+
.test_en_i ( '0 ),
144+
.clk_o ( clk_acc )
142145
);
143146

144147
/*--------------------------------------------------------------*/
@@ -581,10 +584,13 @@ redmule_inst_decoder #(
581584
.InstFifoDepth ( 4 ),
582585
.McnfigOpCode ( McnfigOpCode ),
583586
.MarithOpCode ( MarithOpCode ),
587+
.MopcntOpCode ( MopcntOpCode ),
584588
.McnfigFunct3 ( McnfigFunct3 ),
585589
.MarithFunct3 ( MarithFunct3 ),
590+
.MopcntFunct3 ( MopcntFunct3 ),
586591
.McnfigFunct2 ( McnfigFunct2 ),
587592
.MarithFunct2 ( MarithFunct2 ),
593+
.MopcntFunct2 ( MopcntFunct2 ),
588594
.XifIdWidth ( XifIdWidth ),
589595
.XifNumHarts ( XifNumHarts ),
590596
.XifIssueRegisterSplit ( XifIssueRegisterSplit ),
@@ -622,7 +628,7 @@ fifo_v3 #(
622628
) i_config_fifo (
623629
.clk_i ( clk_acc ),
624630
.rst_ni ( rst_ni ),
625-
.flush_i ( clear ),
631+
.flush_i ( '0 ),
626632
.testmode_i ( '0 ),
627633
.full_o ( config_fifo_full ),
628634
.empty_o ( config_fifo_empty ),

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