[treewide] Remove reduction unit

Author: Andrea Belano

Bender.yml

@@ -46,7 +46,6 @@ sources:
     - rtl/redmule_engine.sv
     - rtl/redmule_top.sv
     - rtl/redmule_memory_scheduler.sv
-    - rtl/redmule_reduction_unit.sv
     - rtl/redmule_mux.sv
     - rtl/redmule_inst_decoder.sv
 

rtl/redmule_ctrl.sv

@@ -45,7 +45,7 @@ module redmule_ctrl
   output cntrl_flags_t            cntrl_flags_o
 );
 
-  logic        clear, latch_clear;
+  logic        latch_clear;
   logic        tiler_setback, tiler_valid;
 
   typedef enum logic [2:0] {
@@ -63,7 +63,7 @@ module redmule_ctrl
   redmule_tiler  i_cfg_tiler (
     .clk_i       ( clk_i          ),
     .rst_ni      ( rst_ni         ),
-    .clear_i     ( clear          ),
+    .clear_i     ( '0             ),
     .setback_i   ( tiler_setback  ),
     .start_cfg_i ( start_cfg_i    ),
     .valid_o     ( tiler_valid    ),
@@ -83,10 +83,7 @@ module redmule_ctrl
     if(~rst_ni) begin
        current <= REDMULE_LATCH_RST;
     end else begin
-      if (clear)
-        current <= REDMULE_IDLE;
-      else
-        current <= next;
+      current <= next;
     end
   end
 
@@ -95,7 +92,7 @@ module redmule_ctrl
     if (~rst_ni) begin
       slave_start <= 1'b0;
     end else begin
-      if (clear || tiler_setback)
+      if (tiler_setback)
         slave_start <= 1'b0;
       else if (start_cfg_i)
         slave_start <= 1'b1;
@@ -142,7 +139,7 @@ module redmule_ctrl
         end
       end
       REDMULE_COMPUTING: begin
-        if (flgs_streamer_i.z_stream_sink_flags.ready_start && fifo_empty_i && ((redmule_config.red_op == RED_NONE) | flgs_streamer_i.r_stream_sink_flags.ready_start)) begin
+        if (flgs_streamer_i.z_stream_sink_flags.ready_start && fifo_empty_i) begin
           next = REDMULE_FINISHED;
         end
       end
@@ -157,7 +154,6 @@ module redmule_ctrl
   /*                            Other combinational assigmnets                                   */
   /*---------------------------------------------------------------------------------------------*/
   assign evt_o   = flgs_streamer_i.z_stream_sink_flags.done;
-  assign clear_o = clear || latch_clear || next == REDMULE_FINISHED;
-  assign clear   = '0;
+  assign clear_o = latch_clear;
 
 endmodule : redmule_ctrl

rtl/redmule_memory_scheduler.sv

@@ -268,35 +268,6 @@ module redmule_memory_scheduler
     cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d2_len = '0;
     cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d3_stride = '0;
     cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.dim_enable_1h = 3'b011;
-
-
-    // FIXME
-    // Here we initialize the streamer source signals
-    // for the R stream source
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.base_addr = config_i.r_addr;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.tot_len = config_i.n_size/W;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.d0_len = '0;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.d0_stride = W*ELW/8;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.d1_len = '0;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.d1_stride = '0;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.d2_stride = '0;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.d2_len = '0;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.d3_stride = '0;
-    cntrl_streamer_o.r_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 3'b000;
-
-    // FIXME
-    // Here we initialize the streamer source signals
-    // for the R stream sink
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.base_addr = config_i.r_addr;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.tot_len = config_i.n_size/W;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.d0_len = '0;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.d0_stride = W*ELW/8;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.d1_len = '0;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.d1_stride = '0;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.d2_stride = '0;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.d2_len = '0;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.d3_stride = '0;
-    cntrl_streamer_o.r_stream_sink_ctrl.addressgen_ctrl.dim_enable_1h = 3'b000;
   end
 
   assign start_x_streamer = (~x_config_empty && ~x_config_full && ~x_done_o) || x_config_full;
@@ -305,9 +276,7 @@ module redmule_memory_scheduler
     cntrl_streamer_o.x_stream_source_ctrl.req_start     = (start_x_streamer || tot_x_read_q != '0 && tot_x_read_q != x_config.tot_x_read) && flgs_streamer_i.x_stream_source_flags.ready_start;
     cntrl_streamer_o.w_stream_source_ctrl.req_start     = ~w_config_empty && flgs_streamer_i.w_stream_source_flags.ready_start;
     cntrl_streamer_o.y_stream_source_ctrl.req_start     = ~y_config_empty && y_config.gemm_selection && flgs_streamer_i.y_stream_source_flags.ready_start;
-    cntrl_streamer_o.r_stream_source_ctrl.req_start     = '0;
     cntrl_streamer_o.z_stream_sink_ctrl.req_start       = ~z_config_empty && flgs_streamer_i.z_stream_sink_flags.ready_start && ~flgs_streamer_i.z_stream_sink_flags.done; // we need the ~done here as this is asserted at the same time as the ready_start signal in sink modules
-    cntrl_streamer_o.r_stream_sink_ctrl.req_start       = '0;
   end
 
   // FIXME

rtl/redmule_mux.sv

@@ -58,10 +58,6 @@ module redmule_mux
       winner_d = YsourceStreamId;
     end else if (in_req[NumStreamSources]) begin   // Z
       winner_d = NumStreamSources;
-    end else if (in_req[RsourceStreamId]) begin    // R Source
-      winner_d = RsourceStreamId;
-    end else if (in_req[NumStreamSources+1]) begin // R Sink
-      winner_d = NumStreamSources+1;
     end
   end
 

rtl/redmule_pkg.sv

@@ -36,52 +36,11 @@ package redmule_pkg;
   parameter int unsigned ECC_N_CHUNK             = DATA_W / ECC_CHUNK_SIZE;
   parameter int unsigned LATCH_BUFFERS           = 0;
 
-  // Register File mapping
-  /**********************
-  ** Slave RF indexing **
-  **********************/
-  parameter int unsigned X_ADDR = 0; // 0x00 /* These do not change between slave and final */
-  parameter int unsigned W_ADDR = 1; // 0x04 /* These do not change between slave and final */
-  parameter int unsigned Z_ADDR = 2; // 0x08 /* These do not change between slave and final */
-  parameter int unsigned MCFIG0 = 3; // 0x0C --> [31:16] -> K size, [15: 0] -> M size
-  parameter int unsigned MCFIG1 = 4; // 0x10 --> [31: 0] -> N Size
-  // Matrix arithmetic config register
-  // [20:20] -> Send X stream
-  // [19:19] -> Receive X stream
-  // [18:18] -> Send W stream
-  // [17:17] -> Receive W stream
-  // [16:16] -> Reduction initialization
-  // [15:14] -> Reduction operation
-  // [12:10] -> Operation selection
-  // [ 9: 7] -> Input/Output format
-  parameter int unsigned MACFG = 5; // 0x14
-  // Reduction initialization values addr
-  parameter int unsigned R_ADDR_R = 6; // 0x18
-
-  parameter bit[6:0] MCNFIG = 7'b0001011; // 0x0B
-  parameter bit[6:0] MARITH = 7'b0101011; // 0x2B
-  parameter bit[6:0] RVCSR  = 7'b1110011; // 0x73 -> RISC-V CSR instruction opcode
-
-  /* The CSRs below are not really present in the current RedMulE version. The following
-     enum is here to allow future development where it might be useful to write the
-     configuration registers through standard `csrw` instructions coming from the core.
-     The CSRs values are chosen following the custom read/write already available in the
-     RISC-V specifications. */
-  typedef enum logic[11:0] {
-    CSR_REDMULE_X_ADDR = 12'h800,
-    CSR_REDMULE_W_ADDR = 12'h801,
-    CSR_REDMULE_Z_ADDR = 12'h802,
-    CSR_REDMULE_MCFIG0 = 12'h803,
-    CSR_REDMULE_MCFIG1 = 12'h804,
-    CSR_REDMULE_MACFG  = 12'h805
-  } redmule_csr_num_e;
-
-  parameter int unsigned NumStreamSources     = 4; // X, W, Y, R
+  parameter int unsigned NumStreamSources     = 3; // X, W, Y
 
   parameter int unsigned XsourceStreamId      = 0;
   parameter int unsigned WsourceStreamId      = 1;
   parameter int unsigned YsourceStreamId      = 2;
-  parameter int unsigned RsourceStreamId      = 3;
 
   typedef enum logic { LD_IN_FMP, LD_WEIGHT } source_sel_e;
   typedef enum logic { LOAD, STORE }          ld_st_sel_e;
@@ -106,9 +65,7 @@ package redmule_pkg;
     hci_package::hci_streamer_flags_t x_stream_source_flags;
     hci_package::hci_streamer_flags_t w_stream_source_flags;
     hci_package::hci_streamer_flags_t y_stream_source_flags;
-    hci_package::hci_streamer_flags_t r_stream_source_flags;
     hci_package::hci_streamer_flags_t z_stream_sink_flags;
-    hci_package::hci_streamer_flags_t r_stream_sink_flags;
   } flgs_streamer_t;
 
   typedef struct packed {
@@ -214,21 +171,6 @@ package redmule_pkg;
     logic idle;
   } cntrl_flags_t;
 
-  typedef enum logic [1:0] { RED_NONE, MAX, SUM } red_op_t;
-
-  typedef struct packed {
-    logic [15:0]  row_len;
-    red_op_t      op;
-    logic         load;
-    logic         enable;
-    logic         ready;
-  } cntrl_red_t;
-
-
-  typedef struct packed {
-    logic is_initialized;
-  } flgs_red_t;
-
   typedef enum logic [2:0] { MATMUL=3'h0, GEMM=3'h1, ADDMAX=3'h2, ADDMIN=3'h3, MULMAX=3'h4, MULMIN=3'h5, MAXMIN=3'h6, MINMAX=3'h7 } gemm_op_e;
   typedef enum logic [1:0] { Float8=2'h0, Float16=2'h1, Float8Alt=2'h2, Float16Alt=2'h3 } gemm_fmt_e;
   typedef enum logic       { RNE=1'h0, RTZ=1'h1 } rnd_mode_e;
@@ -273,8 +215,6 @@ package redmule_pkg;
     fpu_fmt_e computing_format;
     logic        gemm_selection;
     logic [31:0] r_addr;
-    logic        red_init;
-    red_op_t     red_op;
     logic        send_w;
     logic        receive_w;
     logic        send_x;
@@ -315,23 +255,4 @@ package redmule_pkg;
     logic [31:0] data;
   } core_default_data_rsp_t;
 
-  typedef struct packed {
-    logic req;
-    logic wen;
-    logic [DATA_W/8-1:0] be;
-    logic signed [DATA_W/32-1:0][31:0]boffs;
-    logic [31:0] add;
-    logic [DATA_W-1:0] data;
-    logic lrdy;
-    logic user;
-  } redmule_default_data_req_t;
-
-  typedef struct packed {
-    logic gnt;
-    logic r_valid;
-    logic [DATA_W-1:0] r_data;
-    logic r_opc;
-    logic r_user;
-  } redmule_default_data_rsp_t;
-
 endpackage