Add back memory-mapped hwpe-ctrl interface exploiting new SystemRDL register spec#55
Add back memory-mapped hwpe-ctrl interface exploiting new SystemRDL register spec#55FrancescoConti wants to merge 24 commits intoab/xif-1.0from
hwpe-ctrl interface exploiting new SystemRDL register spec#55Conversation
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@belanoa should this be rebased on top of something? I believe on my side the PR is now mature. |
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Pull request overview
This pull request reintroduces a memory-mapped register interface for the RedMulE hardware accelerator, replacing the previous XIF (eXtension Interface) custom instruction approach with a more traditional memory-mapped control interface. The implementation uses SystemRDL specification to automatically generate register interface code via PeakRDL tools, following the same architectural patterns established in the existing XIF interface.
Changes:
- Added new
CtrlIntfConfigparameter to select between XIF and HWPE_TARGET (memory-mapped) control interfaces at elaboration time - Introduced SystemRDL-based register specification and auto-generated register interface modules
- Added
MisalignedAccessSupportparameter for TCDM access configuration, propagated through the streamer hierarchy
Reviewed changes
Copilot reviewed 12 out of 13 changed files in this pull request and generated 8 comments.
Show a summary per file
| File | Description |
|---|---|
| rtl/redmule_top.sv | Adds conditional generation logic to instantiate either XIF decoder or memory-mapped target decoder based on CtrlIntfConfig parameter |
| rtl/redmule_pkg.sv | Defines control interface enum type and misaligned access support default parameter |
| rtl/redmule_streamer.sv | Propagates MisalignedAccessSupport parameter and updates HCI interface instantiations with explicit size parameters |
| rtl/redmule_tiler.sv | Adds assertion to validate DataW parameter relationship |
| rtl/redmule_ctrl.sv | Integrates target_clear_i signal into clear logic |
| rtl/redmule_inst_decoder.sv | Adds extensive inline documentation comments explaining XIF decoder logic (no functional changes) |
| rtl/ctrl/redmule_target_decoder.sv | New module implementing memory-mapped control interface decoder with register-to-config mapping |
| rtl/ctrl/redmule_regif.rdl | SystemRDL specification defining register map for RedMulE control interface |
| rtl/ctrl/regif/redmule_regif_pkg.sv | Auto-generated package containing register interface types |
| rtl/ctrl/regif/redmule_regif.sv | Auto-generated OBI-compatible register interface module |
| rtl/ctrl/gen_regif.sh | Script to generate SystemVerilog and C header files from SystemRDL specification |
| Bender.yml | Updates hwpe-ctrl to version 3.0.0 and hci to version 2.3.0 |
| Bender.lock | Dependency lock file (requires regeneration) |
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These comments are generated by Copilot (Claude Sonnet 4.5) and should be checked, but they do seem legit. This is a preliminary action to reproduce a similar programming interface as XIF in a memory-mapped (hwpe-ctrl) setting.
This renewed register interface mimics identical structure to the XIF that is currently the only supported one on the development branch of RedMulE.
…to redmule_top Also, propagate target_clear to the controller when using HWPE_TARGET interface (XIF currently does not provide a software-based soft clear mechanism, which is a significant liability...)
This reverts commit b748ba1.
…ization and assert safeguards
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
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Hey Francesco, the PR looks great! My only comment is about the HWPE control interface. Should we use explicit signals instead of the interface? This way, we can avoid instantiating a dummy HWPE control interface every time we use the accelerator with the XIF, which is not very elegant and impractical IMO. |
Personally I find the cleanest way to deal with this is to create a |
This pull request reintroduces a memory-mapped register interface for RedMulE, based on a SystemRDL specification. The changes include a SystemRDL file that describes the register map, a script to generate SystemVerilog and C header outputs using PeakRDL, and integration of the generated interface into the hardware design.
The register interface follows the same structure of the XIF interface currently available in the
ab/xif-1.0branch.To-do list before review:
Other actions to-do list (necessary, but can also be pushed to future PRs):