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pulp-platform / snitch_cluster Public

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hw: Add native bootrom#168

Merged

colluca merged 90 commits intomainpulp-platform/snitch_cluster:mainfrom

bootrompulp-platform/snitch_cluster:bootromCopy head branch name to clipboard

Jan 28, 2025

Conversation Commits90 (90)Checks Files changed

Merged

hw: Add native bootrom#168
colluca merged 90 commits intomainfrom
bootrom

Commits

Commits on Jan 22, 2025

Chagned makro names

Thierry Dubochet
authored and
fischeti
committed
Setup Bootrom Generation.

Thierry Dubochet
authored and
fischeti
committed
Bootable Bootrom instantiated.

Thierry Dubochet
authored and
fischeti
committed
Setup Bootrom Generation.

MilosHirsl
authored and
fischeti
committed
Bootable Bootrom instantiated.

MilosHirsl
authored and
fischeti
committed
Linked Bootrom Scratch Register to correct address.

MilosHirsl
authored and
fischeti
committed
Fixed Scratch Register linking address. Modified regfile for synthesis.

MilosHirsl
authored and
fischeti
committed
Modified bootrom to avoid synthesis issues.

MilosHirsl
authored and
fischeti
committed
Moved Bootrom Space into Cluster Peripheral.

MilosHirsl
authored and
fischeti
committed
Changed Scratch Registers Software Permissions to allow Read/Write and set Performance Counters to track Retired Instructions during Boot Procedure.

MilosHirsl
authored and
fischeti
committed
Adjusted assignment size from generated boot data to actual boot size.

MilosHirsl
authored and
fischeti
committed
Fixed assign statement.

MilosHirsl
authored and
fischeti
committed
Modified bootrom after debugging to fetch address at scratch register 1.

MilosHirsl
authored and
fischeti
committed
git: Remove unused config file
fischeti
committed
hw: Don't change reset value of performance counters
fischeti
committed
hw: Fix peripheral reg Makefile
fischeti
committed
git: Remove original files
fischeti
committed
bootrom: Remove old script
fischeti
committed
hw: Clean up bootrom generation
fischeti
committed
util: Move bootrom generation script to util folder
fischeti
committed
Clean up some more
fischeti
committed
lint: Python files
fischeti
committed
lint: Fix missing license headers
fischeti
committed
lint: Other formatting
fischeti
committed
hw: Rename `bootrom` to `snitch_bootrom`
fischeti
committed
hw: Format auto-generated SV sources
fischeti
committed
Revert "hw: Format auto-generated SV sources"
fischeti
committed
hw: Rename scratch registers and disable `hwext` setting
fischeti
committed
bootrom: Enable external interrupts
fischeti
committed
test: Write binary entry point from testbench to scratch1 register
fischeti
committed
lint: C++ sources
fischeti
committed
hw: Fix unused parameters in `axi_to_mem`
fischeti
committed
test: Use simpler AXI driver for compatibility with verilator
fischeti
committed
test: Use simple bootrom that directly jumps to L3
fischeti
committed
cfg: Don't specify `boot_addr`
fischeti
committed
cfg: Specify `boot_rom_size` for all configurations
fischeti
committed
doc: Update `boot_addr` description
fischeti
committed
hw: Rename `BootOrigin` to `BootAddrInternal`
fischeti
committed
misc: Revert unused stuff
fischeti
committed
vlt: Remove `bootrom.cc`
fischeti
committed
banshee: Update addresses
fischeti
committed
tb: Revert small changes
fischeti
committed
bootrom: Don't write author list in auto-generated SV file
fischeti
committed
misc: Fix comments and formatting
fischeti
committed
Revert "Chagned makro names"
fischeti
committed
cfg: Update `dma_mchan` config
fischeti
committed
cfg: Remove unused `boot_addr` in configs
fischeti
committed
cfg: Remove obsolete quadrant config
fischeti
committed
cfg: Add `boot_rom_size` config
fischeti
committed
cfg: Rename `boot_rom_size` to `bootrom_size`
fischeti
committed
hw: Add bootrom generation to `rtl` target
fischeti
committed
hw: Update sources
fischeti
committed
bootrom: Use clang to compile bootrom
fischeti
committed
hw: Parametrize internal bootorm
fischeti
committed
bootrom: Revert to initial bootrom
fischeti
committed
test: Bundle VIP in a module
fischeti
committed
Remove .rtlbinary
fischeti
committed
bootrom: Use correct output target
fischeti
committed
make: Add verilator bender target for Verilator compilation
fischeti
committed
vlt: Get rid of clk/rst generator inside verilator
fischeti
committed
test: Get binary entry from fesvr
fischeti
committed
vip: Rename `set_msip` task
fischeti
committed
test: Increase wait time until sending an interrupt
fischeti
committed
sim: Don't show loading messages when starting vsim
fischeti
committed
tpl: Expose address sizes
fischeti
committed
cfg: Indent lines
fischeti
committed
hw: Remove Makefile from peripherals
fischeti
committed
lint SV sources
fischeti
committed
container: Update verilator version
fischeti
committed
hw: Fix non-bootrom configurations
fischeti
committed
sw: Fix base address of peripherals
fischeti
committed
hw: Try to fix elaboration
fischeti
committed
env: Bump VCS and Questa versions
fischeti
committed

Commits on Jan 23, 2025

sw: Fix perf_cnt test
fischeti
committed
Revert "sw: Fix perf_cnt test"
fischeti
committed
sw: Fix address map
fischeti
committed
bootrom: Remove l3 base
fischeti
committed
banshee: Fix cl_clint address in config
fischeti
committed
hw: Clarify parameter comments
fischeti
committed
vlt: Use verilator from oseda environment
fischeti
committed

Commits on Jan 24, 2025

ci: Use oseda environment for vlt compilation
fischeti
committed
vlt: Clean up verilator build
fischeti
committed
Revert "ci: Use oseda environment for vlt compilation"
fischeti
committed
vlt: Wrap simulation binary in script
fischeti
committed
vlt: Use absolute path of verilator binary in the wrapper
fischeti
committed

Commits on Jan 27, 2025

vlt: Pass additional variables for IPC
fischeti
committed
ipc: Allocate enough size for nullcharacter
fischeti
committed
test: Implement `get_bin_entry` for verilator without using bootdata
fischeti
committed
util: Move bootrom generation script
fischeti
committed
treewide: Final revision, minor formatting changes and software bug fix
colluca
committed

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