pbio/drv/reset/reset_ev3: Implement reset via watchdog timer

Author: ArcaneNibble

lib/pbio/drv/reset/reset_ev3.c

@@ -10,10 +10,17 @@
 #include <pbdrv/reset.h>
 #include <pbdrv/gpio.h>
 
+#include <tiam1808/hw/hw_types.h>
+#include <tiam1808/hw/soc_AM1808.h>
+#include <tiam1808/timer.h>
+
 #include "../drv/gpio/gpio_ev3.h"
 
 #include <tiam1808/hw/hw_syscfg0_AM1808.h>
 
+#define BOOTLOADER_UPDATE_MODE_ADDR     0xFFFF1FFC
+#define BOOTLOADER_UPDATE_MODE_VALUE    0x5555AAAA
+
 static const pbdrv_gpio_t poweroff_pin = PBDRV_GPIO_EV3_PIN(13, 19, 16, 6, 11);
 
 void pbdrv_reset_init(void) {
@@ -23,17 +30,31 @@ void pbdrv_reset_init(void) {
 void pbdrv_reset(pbdrv_reset_action_t action) {
     for (;;) {
         switch (action) {
-            case PBDRV_RESET_ACTION_RESET_IN_UPDATE_MODE:
-                // TODO
+            case PBDRV_RESET_ACTION_POWER_OFF:
+                pbdrv_reset_power_off();
                 break;
-            // TODO: implement case PBDRV_RESET_ACTION_RESET
+            case PBDRV_RESET_ACTION_RESET_IN_UPDATE_MODE:
+                *(volatile uint32_t *)BOOTLOADER_UPDATE_MODE_ADDR = BOOTLOADER_UPDATE_MODE_VALUE;
+            // Fall through
             default:
+                // PBDRV_RESET_ACTION_RESET
+
+                // Configure watchdog timer
+                TimerDisable(SOC_TMR_1_REGS, TMR_TIMER_BOTH);
+                TimerConfigure(SOC_TMR_1_REGS, TMR_CFG_64BIT_WATCHDOG);
+                TimerPeriodSet(SOC_TMR_1_REGS, TMR_TIMER12, 0);
+                TimerPeriodSet(SOC_TMR_1_REGS, TMR_TIMER34, 0);
+                TimerWatchdogActivate(SOC_TMR_1_REGS);
+
+                // Poke the watchdog timer with a bad value to immediately trigger it
+                HWREG(SOC_TMR_1_REGS + TMR_WDTCR) = 0;
                 break;
         }
     }
 }
 
 pbdrv_reset_reason_t pbdrv_reset_get_reason(void) {
+    // There is no easy way to determine the reset reason on this platform
     return PBDRV_RESET_REASON_NONE;
 }