pbio/drv/pwm/pwm_ev3: Load PRU firmware which implements LED PWM

Author: ArcaneNibble

bricks/_common/arm_none_eabi.mk

@@ -564,6 +564,7 @@ OBJ += $(addprefix $(BUILD)/, $(TI_AM1808_USB_SRC_C:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(EV3_SRC_S:.S=.o))
 $(addprefix $(BUILD)/, $(EV3_SRC_S:.S=.o)): CFLAGS += -D__ASSEMBLY__
 OBJ += $(BUILD)/pru_suart.bin.o
+OBJ += $(BUILD)/pru_ledpwm.bin.o
 endif
 
 # List of sources for qstr extraction
@@ -637,6 +638,11 @@ $(BUILD)/u-boot.bin:
 	$(Q)mkdir -p $(dir $@)
 	$(Q)curl -sL -o $@ https://github.com/pybricks/u-boot/releases/download/pybricks/v2.0.1/u-boot.bin
 	$(Q)echo "86ddad84f64d8aea85b4315fc1414bdec0bb0d46c92dbd3db45ed599e3a994cb  $@" | sha256sum -c --strict
+$(BUILD)/pru_ledpwm.bin:
+	$(ECHO) "Downloading pru_ledpwm.bin"
+	$(Q)mkdir -p $(dir $@)
+	$(Q)curl -sL -o $@ https://github.com/pybricks/pybricks-pru/releases/download/v0.0.1/pru_ledpwm.bin
+	$(Q)echo "c0138addb8ebb3d0f531499b6f45ccc71f524afbb6ce55ca3ab462a001ec28d2  $@" | sha256sum -c --strict
 
 MAKE_BOOTABLE_IMAGE = $(PBTOP)/bricks/ev3/make_bootable_image.py
 
@@ -668,6 +674,9 @@ $(BUILD)/firmware.zip: $(ZIP_FILES)
 $(BUILD)/pru_suart.bin.o: $(PBTOP)/lib/pbio/drv/uart/uart_ev3_pru_lib/pru_suart.bin
 	$(Q)$(OBJCOPY) -I binary -O elf32-littlearm -B arm \
 		--rename-section .data=.pru0,alloc,load,readonly,data,contents $^ $@
+$(BUILD)/pru_ledpwm.bin.o: $(BUILD)/pru_ledpwm.bin
+	$(Q)$(OBJCOPY) -I binary -O elf32-littlearm -B arm \
+		--rename-section .data=.pru1,alloc,load,readonly,data,contents $^ $@
 
 # firmware in DFU format
 $(BUILD)/%.dfu: $(BUILD)/%-base.bin

lib/pbio/drv/pwm/pwm_ev3.c

@@ -11,38 +11,71 @@
 #include <pbdrv/gpio.h>
 #include <pbio/error.h>
 
+#include <tiam1808/hw/hw_syscfg0_AM1808.h>
+#include <tiam1808/hw/hw_types.h>
+#include <tiam1808/hw/soc_AM1808.h>
+#include <tiam1808/pruss.h>
+#include <tiam1808/psc.h>
+#include <tiam1808/timer.h>
+
 #include "../drv/pwm/pwm.h"
 #include "../../drv/pwm/pwm_ev3.h"
 #include "../../drv/gpio/gpio_ev3.h"
 
+// This is the second 64K of the on-chip RAM
+#define PRU1_SHARED_RAM_ADDR    0x80010000
+
+// This needs to match the interface expected by the PRU firmware
+typedef struct shared_ram {
+    uint8_t pwms[4];
+} shared_ram;
+static volatile shared_ram *const pru1_shared_ram = (volatile shared_ram *)PRU1_SHARED_RAM_ADDR;
+
 static pbio_error_t pbdrv_pwm_tiam1808_set_duty(pbdrv_pwm_dev_t *dev, uint32_t ch, uint32_t value) {
-    // Blue not available.
-    if (ch == 2) {
-        return PBIO_SUCCESS;
-    }
-    pbdrv_pwm_tiam1808_platform_data_t *priv = dev->priv;
-
-    // TODO: implement PWM. Just use GPIO for now.
-    pbdrv_gpio_t *gpio = (ch == 0) ? &priv->gpio_red : &priv->gpio_green;
-    if (value) {
-        pbdrv_gpio_out_high(gpio);
-    } else {
-        pbdrv_gpio_out_low(gpio);
-    }
+    // TODO: Reimplement this function to use the PRU
     return PBIO_SUCCESS;
 }
 
 static const pbdrv_pwm_driver_funcs_t pbdrv_pwm_tiam1808_funcs = {
     .set_duty = pbdrv_pwm_tiam1808_set_duty,
 };
 
+extern char _pru1_start;
+extern char _pru1_end;
+
 void pbdrv_pwm_tiam1808_init(pbdrv_pwm_dev_t *devs) {
+    // Enable Timer0 "34" half to count up to 256 * 256
+    // This is used by the PRU to time the PWM
+    TimerPreScalarCount34Set(SOC_TMR_0_REGS, 0);
+    TimerPeriodSet(SOC_TMR_0_REGS, TMR_TIMER34, 256 * 256 - 1);
+    TimerEnable(SOC_TMR_0_REGS, TMR_TIMER34, TMR_ENABLE_CONT);
+
+    // Set GPIO alt modes for the PRU
+    pbdrv_gpio_alt(&pbdrv_pwm_tiam1808_platform_data[0].gpio_red, SYSCFG_PINMUX13_PINMUX13_11_8_PRU1_R30_12);
+    pbdrv_gpio_alt(&pbdrv_pwm_tiam1808_platform_data[0].gpio_green, SYSCFG_PINMUX14_PINMUX14_3_0_PRU1_R30_10);
+    pbdrv_gpio_alt(&pbdrv_pwm_tiam1808_platform_data[1].gpio_red, SYSCFG_PINMUX13_PINMUX13_15_12_PRU1_R30_11);
+    pbdrv_gpio_alt(&pbdrv_pwm_tiam1808_platform_data[1].gpio_green, SYSCFG_PINMUX13_PINMUX13_7_4_PRU1_R30_13);
+
+    // TODO: Remove this test code
+    pru1_shared_ram->pwms[0] = 0x20;    // R
+    pru1_shared_ram->pwms[1] = 0xc0;    // G
+    pru1_shared_ram->pwms[2] = 0x10;    // R
+    pru1_shared_ram->pwms[3] = 0xf0;    // G
+
+    // Enable PRU1 and load its firmware
+    PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_PRU, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
+    PRUSSDRVPruDisable(1);
+    PRUSSDRVPruReset(1);
+    unsigned int *fw_start = (unsigned int *)&_pru1_start;
+    uint32_t fw_sz = &_pru1_end - &_pru1_start;
+    PRUSSDRVPruWriteMemory(PRUSS0_PRU1_IRAM, 0, fw_start, fw_sz);
+    // Set constant table C30 to point to 0x80010000
+    HWREG(PRU1CONTROL_PHYS_BASE + 0x2c) = (PRU1_SHARED_RAM_ADDR >> 8) & 0xffff;
+    PRUSSDRVPruEnable(1);
+
     for (int i = 0; i < PBDRV_CONFIG_PWM_TIAM1808_NUM_DEV; i++) {
         devs[i].funcs = &pbdrv_pwm_tiam1808_funcs;
         devs[i].priv = (pbdrv_pwm_tiam1808_platform_data_t *)&pbdrv_pwm_tiam1808_platform_data[i];
-
-        pbdrv_gpio_out_low(&pbdrv_pwm_tiam1808_platform_data[i].gpio_red);
-        pbdrv_gpio_out_low(&pbdrv_pwm_tiam1808_platform_data[i].gpio_green);
     }
 }
 

lib/pbio/platform/ev3/platform.ld

@@ -38,6 +38,10 @@ SECTIONS
         KEEP(*(.pru0));
         . = ALIGN(4);
         _pru0_end = .;
+        _pru1_start = .;
+        KEEP(*(.pru1));
+        . = ALIGN(4);
+        _pru1_end = .;
     } >DDR
 
     .data :