[EV3] Initial MMU enablement #363
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dlech
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Aug 1, 2025
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Done. I added a |
These transfers allow reading "characteristics" which would otherwise be exchanged over BLE GATT. They contain information about the firmware version and hub capabilities. Also move the bRequest values into pbio/protocol.h so they can be shared
In order to be able to detect disconnection, we cannot force device mode in the PHY. Forcing device mode overrides the analog comparators used to detect VBUS. Not forcing device mode should be fine because device mode is the default (enabling host mode requires setting DEVCTL.SESSION explicitly, and the ID pin is explicitly disconnected on the EV3 PCB.)
This handles Pybricks commands, status flag reporting, and timeouts. stdout is not yet handled.
This replaces the old stopgap stdout logic with stdio over USB
Without this timer, if the hub state doesn't change and the user program doesn't output anything, the hub won't be able to detect that the host software has closed (because it never sends anything which could time out). Keeping this state reasonably up-to-date is important for the hub auto-power-off functionality.
The EV3 technically has an IO port power control, but it doesn't only control the main peripheral ports but also the ADC and USB. It also doesn't require quirk handling to be able to power-cycle the ports. Make this feature compile-time optional rather than having dummy values. This was previously silently dereferencing a null pointer.
Otherwise this dereferences a null pointer.
The MMU was being previously left on by U-boot. Turn it off before starting the system.
This creates an identity mapping for only the valid bits of the address space. It also adds logic to the exception handler to print out fault addresses. This currently marks the entire address space as uncacheable. Drivers will need to be updated to take caches into account before we can mark RAM as cacheable.
This makes sure that we can never take a TLB miss penalty when accessing MMIO or local RAM. These "lockdown" TLB entries are not used by general-purpose operating systems like Linux, and they are entirely separate from the "normal" TLB entries.
The actual faulting instruction for these exceptions is offset (due to CPU pipelining in this core, later as part of compatibility). Print the actual faulting instruction address so that the developer doesn't have to manually subtract 8.
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This code enables the MMU and configures it to trap very-invalid memory accesses. It also currently marks the entire address space as uncacheable until drivers can be updated to properly flush data out of cache.
Previously, U-boot was leaving the MMU enabled, with page tables at the end of DRAM at 0xC3FF0000
This also fixes some invalid pointers that were discovered along the way.