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We are going to be keeping this cache/MMU disable code, so update the comment appropriately.

Also explain what the bit 13 in the control register does.

We are going to be keeping this cache/MMU disable code, so
update the comment appropriately.

Also explain what the bit 13 in the control register does.
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coverage: 56.979% (+0.01%) from 56.965%
when pulling a58a168 on ArcaneNibble:ev3-startup
into 7d9b601 on pybricks:master.

@dlech dlech merged commit 0c1271f into pybricks:master Aug 6, 2025
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dlech commented Aug 6, 2025

Thanks!

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3 participants