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target: family: lpc5500: pre-reset via debug mailbox in reset_and_halt#1919

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fbnors:fix/lpc5500-dm-pre-reset
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target: family: lpc5500: pre-reset via debug mailbox in reset_and_halt#1919
fbnors wants to merge 1 commit intopyocd:developfrom
fbnors:fix/lpc5500-dm-pre-reset

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@fbnors fbnors commented Feb 24, 2026

On LPC55xx devices, running firmware can cause AHB bus contention that makes SWD accesses via the AHB-AP fail with WAIT ACK responses. This leads to transfer timeouts during the flash controller probing and SYSRESETREQ sequences that reset_and_halt performs before flash programming.

The debug mailbox (AP#2) has a dedicated path that does not go through the AHB bus. By issuing a chip reset through the debug mailbox and immediately halting the core at the start of reset_and_halt, all peripherals return to their power-on state and subsequent AHB-dependent operations proceed reliably.

On LPC55xx devices, running firmware can cause AHB bus contention that
makes SWD accesses via the AHB-AP fail with WAIT ACK responses. This
leads to transfer timeouts during the flash controller probing and
SYSRESETREQ sequences that reset_and_halt performs before flash
programming.

The debug mailbox (AP#2) has a dedicated path that does not go through
the AHB bus. By issuing a chip reset through the debug mailbox and
immediately halting the core at the start of reset_and_halt, all
peripherals return to their power-on state and subsequent AHB-dependent
operations proceed reliably.
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