File tree Expand file tree Collapse file tree 1 file changed +3
-2
lines changed
Expand file tree Collapse file tree 1 file changed +3
-2
lines changed Original file line number Diff line number Diff line change 88
99from qiling .arch .arm_const import reg_map as arm_regs
1010from qiling .arch .arm64_const import reg_map as arm64_regs
11- from qiling .arch .mips_const import reg_map as mips_regs
11+ from qiling .arch .mips_const import reg_map as mips_regs_gpr
12+ from qiling .arch .mips_const import reg_map_fpu as mips_regs_fpu
1213from qiling .arch .x86_const import reg_map_16 as x86_regs_16
1314from qiling .arch .x86_const import reg_map_32 as x86_regs_32
1415from qiling .arch .x86_const import reg_map_64 as x86_regs_64
@@ -83,7 +84,7 @@ def load_regsmap(archtype: QL_ARCH) -> Sequence[RegEntry]:
8384 QL_ARCH .ARM : arm_regs ,
8485 QL_ARCH .CORTEX_M : arm_regs ,
8586 QL_ARCH .ARM64 : arm64_regs ,
86- QL_ARCH .MIPS : mips_regs
87+ QL_ARCH .MIPS : dict ( ** mips_regs_gpr , ** mips_regs_fpu )
8788 }[archtype ]
8889
8990 regmap = []
You can’t perform that action at this time.
0 commit comments