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Qcs615 dt add gpu #229

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Qcs615 dt add gpu #229

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1b6c1e7
FROMLIST: arm64: dts: qcom: sm6150: add the GPU SMMU node
quic-qqzhou Nov 21, 2025
d094561
FROMLIST: arm64: dts: qcom: sm6150: Add gpu and rgmu nodes
Nov 21, 2025
e960f78
FROMLIST: arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
Nov 21, 2025
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8 changes: 8 additions & 0 deletions arch/arm64/boot/dts/qcom/qcs615-ride.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -358,6 +358,14 @@
};
};

&gpu {
status = "okay";
};

&gpu_zap_shader {
firmware-name = "qcom/qcs615/a612_zap.mbn";
};

&i2c2 {
clock-frequency = <400000>;
status = "okay";
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141 changes: 141 additions & 0 deletions arch/arm64/boot/dts/qcom/talos.dtsi
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Expand Up @@ -508,6 +508,11 @@
reg = <0x0 0x95900000 0x0 0x1e00000>;
no-map;
};

pil_gpu_mem: pil-gpu@97715000 {
reg = <0x0 0x97715000 0x0 0x2000>;
no-map;
};
};

soc: soc@0 {
Expand Down Expand Up @@ -1687,6 +1692,117 @@
};
};

gpu: gpu@5000000 {
compatible = "qcom,adreno-612.0", "qcom,adreno";
reg = <0x0 0x05000000 0x0 0x90000>,
<0x0 0x0509e000 0x0 0x1000>,
<0x0 0x05061000 0x0 0x800>;
reg-names = "kgsl_3d0_reg_memory",
"cx_mem",
"cx_dbgc";

clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>;
clock-names = "core";

interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "gfx-mem";

iommus = <&adreno_smmu 0x0 0x401>;

operating-points-v2 = <&gpu_opp_table>;
power-domains = <&rpmhpd RPMHPD_CX>;

qcom,gmu = <&gmu>;

#cooling-cells = <2>;

status = "disabled";

gpu_zap_shader: zap-shader {
memory-region = <&pil_gpu_mem>;
};

gpu_opp_table: opp-table {
compatible = "operating-points-v2";

opp-845000000 {
opp-hz = /bits/ 64 <845000000>;
required-opps = <&rpmhpd_opp_turbo>;
opp-peak-kBps = <7050000>;
};

opp-745000000 {
opp-hz = /bits/ 64 <745000000>;
required-opps = <&rpmhpd_opp_nom_l1>;
opp-peak-kBps = <6075000>;
};

opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <5287500>;
};

opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
opp-peak-kBps = <3975000>;
};

opp-435000000 {
opp-hz = /bits/ 64 <435000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <3000000>;
};

opp-290000000 {
opp-hz = /bits/ 64 <290000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1762500>;
};
};
};

gmu: gmu@506a000 {
compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
reg = <0x0 0x0506a000 0x0 0x34000>;

clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
clock-names = "gmu",
"cxo",
"axi",
"memnoc",
"smmu_vote";

power-domains = <&gpucc CX_GDSC>,
<&gpucc GX_GDSC>;
power-domain-names = "cx",
"gx";

interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "oob",
"gmu";

operating-points-v2 = <&gmu_opp_table>;

gmu_opp_table: opp-table {
compatible = "operating-points-v2";

opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
};
};

gpucc: clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0 0x05090000 0 0x9000>;
Expand All @@ -1700,6 +1816,31 @@
#power-domain-cells = <1>;
};

adreno_smmu: iommu@50a0000 {
compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x050a0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
clock-names = "mem",
"hlos",
"iface";
power-domains = <&gpucc CX_GDSC>;
dma-coherent;
};

stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x06002000 0x0 0x1000>,
Expand Down