Talos support port back #341
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GMU registers are always at a fixed offset from the GPU base address, a consistency maintained at least within a given architecture generation. In A8x family, the base address of the GMU has changed, but the offsets of the gmu registers remain largely the same. To enable reuse of the gmu code for A8x chipsets, update the gmu register offsets to be relative to the GPU's base address instead of GMU's. Signed-off-by: Akhil P Oommen <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/689010/ Message-ID: <[email protected]> Signed-off-by: Rob Clark <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Some GPUs like A612 doesn't use a named register range resource. This is because the reg-name property is discouraged when there is just a single resource. To address this, retrieve the 'gmu' register range by its index. It is always guaranteed to be at index 0. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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Port back two patchs for talos a612 chip. Rebase GMU register offsets.