CMOS Register File

Overview

This project presents a full custom CMOS implementation of a 13 × 16 register file, designed and verified at the transistor level. The register file supports one synchronous write port and two asynchronous read ports, and operates correctly at 1 GHz.

The entire design was built from scratch, following a strict hierarchical design methodology, starting from basic logic gates and composing them into progressively more complex functional blocks.

Design Methodology

The register file was developed using a bottom-up, hierarchical approach:

• Primitive logic gates were first designed at the transistor level, including:

  • Inverters
  • AND, OR, and XOR gates

• These gates were composed into higher-level building blocks such as:

  • Multiplexers
  • Address decoders
  • Master–slave D flip-flops

• Flip-flops were then combined to form:

  • 16-bit registers

• Finally, the full 13-entry register file was assembled using the register array, write decoder, read multiplexers, and write-enable gating logic.

This hierarchical structure improves design clarity, reuse, and verification, and closely reflects standard ASIC design practices.

Circuit Implementation

• Logic style: Static CMOS
• Storage elements: Master–slave D flip-flops
• Word width: 16 bits
• Number of registers: 13
• Write behavior: Synchronous (positive clock edge)
• Read behavior: Asynchronous (purely combinational)
• Supply voltage: 1.2 V

All interconnect, including power and ground, was explicitly routed to ensure realistic parasitic effects.

Simulation and Verification

Functional correctness and performance were verified using HSPICE simulations. The design was tested for:

• Correct write and read functionality
• Timing correctness under realistic loading
• Stable operation at 1 GHz clock frequency
• Energy measurements for read and write activity

Post-layout simulations include extracted parasitics to capture interconnect capacitance and coupling effects.

Physical Design

• Full custom layout created from the transistor level
• DRC and LVS clean
• Hierarchical layout mirrors schematic hierarchy

Key Highlights

• Fully custom CMOS design, built entirely from scratch
• No reliance on pre-built logic or register macros
• Hierarchical, reusable architecture
• Verified at 1 GHz with post-layout parasitics
• Representative of real ASIC register file design workflows

Tools

• Cadence Virtuoso (schematic and layout)
• HSPICE (simulation and timing verification)