Add RISC-V fileless fetch payload support#21236
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Add riscv64le and riscv32le architecture support to the fileless
fetch payload adapter. This enables in-memory ELF execution via
memfd_create on RISC-V Linux targets without writing to disk.
The first-stage shellcode (52 bytes, 13 instructions) performs:
memfd_create("") -> ftruncate(fd, 0) -> getpid() -> kill(pid, SIGSTOP)
Uses getpid + kill(SIGSTOP) instead of pause, as pause is not
available in the asm-generic syscall table used by RISC-V. This
matches the existing aarch64 approach.
The jump stub uses auipc + ld/lw + jalr to load and branch to an
absolute address embedded after the instruction sequence (20 bytes
for rv64, 16 bytes for rv32).
Only RV32I/RV64I base integer instructions are used. The sole
difference between the two variants is sd vs sw for the stack
store.
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Add riscv64le and riscv32le architecture support to the fileless fetch payload adapter. This enables in-memory ELF execution via memfd_create on RISC-V Linux targets without writing to disk.
The first-stage shellcode (52 bytes, 13 instructions) performs:
memfd_create("") -> ftruncate(fd, 0) -> getpid() -> kill(pid, SIGSTOP)
Uses getpid + kill(SIGSTOP) instead of pause, as pause is not available in the asm-generic syscall table used by RISC-V. This matches the existing aarch64 approach.
The jump stub uses auipc + ld/lw + jalr to load and branch to an absolute address embedded after the instruction sequence (20 bytes for rv64, 16 bytes for rv32).
Only RV32I/RV64I base integer instructions are used. The sole difference between the two variants is sd vs sw for the stack store.
Verification
Set up the handler with a fileless fetch payload:
Generate fetch command:
Run the generated command on a RISC-V system. You should get a session.