drm: rp1: rp1-vec: First attempt at using "field wobble "for interlace

This works around the 30fps limitation when using VEC's "native"
interlaced modes in the front end. The technique is adapted from
the RP1 DPI driver (DPI does not have a native interlaced mode).

Some register changes were required in the VEC back end to make
this work, in particular for NTSC timings.

Signed-off-by: Nick Hollinghurst <[email protected]>

Author: njhollinghurst

drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c

@@ -470,6 +470,7 @@ static int rp1vec_platform_probe(struct platform_device *pdev)
 		return ret;
 	}
 	vec->pdev = pdev;
+	spin_lock_init(&vec->hw_lock);
 
 	for (i = 0; i < RP1VEC_NUM_HW_BLOCKS; i++) {
 		vec->hw_base[i] =

drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h

@@ -50,6 +50,12 @@ struct rp1_vec {
 	u32 cur_fmt;
 	bool fake_31khz, vec_running, pipe_enabled;
 	struct completion finished;
+
+	spinlock_t hw_lock; /* the following are used in line-match ISR */
+	dma_addr_t last_dma_addr;
+	u32 last_stride;
+	bool interlaced;
+	bool lower_field_flag;
 };
 
 /* ---------------------------------------------------------------------- */

drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c

@@ -22,6 +22,9 @@
 #define VEC_WRITE(reg, val) writel((val), vec->hw_base[RP1VEC_HW_BLOCK_VEC] + (reg ## _OFFSET))
 #define VEC_READ(reg)	    readl(vec->hw_base[RP1VEC_HW_BLOCK_VEC] + (reg ## _OFFSET))
 
+/* Experimental mode for interlace with 60fps buffer flips */
+#define FIELD_WOBBLE
+
 static void rp1vec_write_regs(struct rp1_vec *vec, u32 offset, u32 const *vals, u32 num)
 {
 	while (num--) {
@@ -168,12 +171,29 @@ static const struct rp1vec_hwmode rp1vec_hwmodes[3][2] = {
 			.scale_burst_chroma = 0x11195561,
 			.misc = 0x00094c02, /* 5-tap FIR, SEQ_EN, 2 flds, 4 fld sync, ilace */
 			.nco_freq = 0x087c1f07c1f07c1f,
+#ifdef FIELD_WOBBLE
+			/*
+			 * NOTE: For the "field-wobble" interlace technique
+			 * (used to achieve 60fps buffer-flip rate) to work,
+			 * we had to offset the vertical timings so that VSYNC
+			 * starts at half-line 0; all image line numbers are
+			 * reduced by 3 compared to NTSC standard numbering.
+			 * This should have no effect on the actual frame.
+			 */
+			.timing_regs = {
+				0x03e10cc6, 0x0d6801fb, 0x023d034c, 0x00f80b6d,
+				0x0207020c, 0x00000005, 0x0006000b, 0x00070104,
+				0x010e020a, 0x00000000, 0x00000000, 0x0119020a,
+				0x00120103, 0x01040118,
+			},
+#else
 			.timing_regs = {
 				0x03e10cc6, 0x0d6801fb, 0x023d034c, 0x00f80b6d,
 				0x00000005, 0x0006000b, 0x000c0011, 0x000a0107,
 				0x0111020d, 0x00000000, 0x00000000, 0x011c020d,
 				0x00150106, 0x0107011b,
 			},
+#endif
 		},
 	}, {
 		/* PAL */
@@ -268,7 +288,7 @@ static const struct rp1vec_hwmode rp1vec_hwmodes[3][2] = {
 			.nco_freq = 0x0879bbf8d6d33ea8,
 			.timing_regs = {
 				0x03e10cc6, 0x0d6801fb, 0x023c034c, 0x00f80b6e,
-				0x00140019, 0x00000005, 0x0006000b, 0x00090103,
+				0x00140019, 0x00000005, 0x0006000b, 0x00090103, // XXX [0x94] looks dodgy to me?
 				0x010f0209, 0x00080102, 0x010e020a, 0x0119020a,
 				0x00120103, 0x01040118,
 			},
@@ -460,8 +480,11 @@ void rp1vec_hw_setup(struct rp1_vec *vec,
 		  BITS(VEC_MODE_VBP_EN, (hwm->max_rows_per_field > h + vpad_b)) |
 		  BITS(VEC_MODE_HFP_EN, (hpad_r > 0))				|
 		  BITS(VEC_MODE_HBP_EN, (wmax > w + hpad_r))			|
+#ifndef FIELD_WOBBLE  /* Clear these for field-wobble! */
 		  BITS(VEC_MODE_FIELDS_PER_FRAME_MINUS1, hwm->interlaced)	|
-		  BITS(VEC_MODE_FIRST_FIELD_ODD, hwm->first_field_odd));
+		  BITS(VEC_MODE_FIRST_FIELD_ODD, hwm->first_field_odd)          |
+#endif
+		  0);
 
 	/* Configure the hardware "back end" (in the VDAC clock domain) */
 	VEC_WRITE(VEC_DAC_80,
@@ -492,6 +515,9 @@ void rp1vec_hw_setup(struct rp1_vec *vec,
 	VEC_WRITE(VEC_DAC_CC, (tvstd >= DRM_MODE_TV_MODE_SECAM) ? 0 : hwm->scale_burst_chroma);
 	VEC_WRITE(VEC_DAC_D0, 0x02000000); /* ADC offsets -- not needed in RP1? */
 	misc = hwm->misc;
+#ifdef FIELD_WOBBLE
+	misc &= ~2; /* For field-wobble: Clear the "fields_per_frame_minus1" flag! */
+#endif
 	if ((tvstd == DRM_MODE_TV_MODE_NTSC_443 || tvstd == DRM_MODE_TV_MODE_PAL) &&
 	    mode_family != 1) {
 		/* Change colour carrier frequency to 4433618.75 Hz; disable hard sync */
@@ -509,6 +535,15 @@ void rp1vec_hw_setup(struct rp1_vec *vec,
 	VEC_WRITE(VEC_DAC_EC, misc | rp1vec_rate_shift_table[rate - 4]);
 	rp1vec_write_regs(vec, 0xDC, rp1vec_fir_regs, ARRAY_SIZE(rp1vec_fir_regs));
 
+#ifdef FIELD_WOBBLE
+	vec->interlaced = hwm->interlaced;
+	vec->lower_field_flag = hwm->first_field_odd;
+#else
+	vec->interlaced = false;
+	vec->lower_field_flag = false;
+#endif
+	vec->last_dma_addr = 0;
+
 	/* Set up interrupts and initialise VEC. It will start on the next rp1vec_hw_update() */
 	VEC_WRITE(VEC_IRQ_FLAGS, 0xFFFFFFFFu);
 	rp1vec_hw_vblank_ctrl(vec, 1);
@@ -525,32 +560,48 @@ void rp1vec_hw_setup(struct rp1_vec *vec,
 
 void rp1vec_hw_update(struct rp1_vec *vec, dma_addr_t addr, u32 offset, u32 stride)
 {
+	unsigned long flags;
+
+	spin_lock_irqsave(&vec->hw_lock, flags);
+
 	/*
 	 * Update STRIDE, DMAH and DMAL only. When called after rp1vec_hw_setup(),
 	 * DMA starts immediately; if already running, the buffer will flip at
-	 * the next vertical sync event.
+	 * the next vertical sync event. In interlaced mode, we need to adjust
+	 * the address and stride to display only the current field, saving
+	 * the original address (so it can be flipped for subsequent fields).
 	 */
-	u64 a = addr + offset;
-
-	if (vec->fake_31khz) {
-		a += stride;
+	addr += offset;
+	vec->last_dma_addr = addr;
+	vec->last_stride = stride;
+	if (vec->fake_31khz || vec->interlaced) {
+		if (vec->fake_31khz || vec->lower_field_flag)
+			addr += stride;
 		stride *= 2;
 	}
 	VEC_WRITE(VEC_DMA_STRIDE, stride);
-	VEC_WRITE(VEC_DMA_ADDR_H, a >> 32);
-	VEC_WRITE(VEC_DMA_ADDR_L, a & 0xFFFFFFFFu);
+	VEC_WRITE(VEC_DMA_ADDR_H, addr >> 32);
+	VEC_WRITE(VEC_DMA_ADDR_L, addr & 0xFFFFFFFFu);
+
+	spin_unlock_irqrestore(&vec->hw_lock, flags);
 }
 
 void rp1vec_hw_stop(struct rp1_vec *vec)
 {
+	unsigned long flags;
+
 	/*
 	 * Stop DMA by turning off the Auto-Repeat flag, and wait up to 100ms for
 	 * the current and any queued frame to end. "Force drain" flags are not used,
 	 * as they seem to prevent DMA from re-starting properly; it's safer to wait.
 	 */
 
+	spin_lock_irqsave(&vec->hw_lock, flags);
+	vec->last_dma_addr = 0;
 	reinit_completion(&vec->finished);
 	VEC_WRITE(VEC_CONTROL, 0);
+	spin_unlock_irqrestore(&vec->hw_lock, flags);
+
 	if (!wait_for_completion_timeout(&vec->finished, HZ / 10))
 		drm_err(&vec->drm, "%s: timed out waiting for idle\n", __func__);
 	VEC_WRITE(VEC_IRQ_ENABLES, 0);
@@ -561,7 +612,10 @@ void rp1vec_hw_vblank_ctrl(struct rp1_vec *vec, int enable)
 	VEC_WRITE(VEC_IRQ_ENABLES,
 		  BITS(VEC_IRQ_ENABLES_DONE, 1) |
 		  BITS(VEC_IRQ_ENABLES_DMA, (enable ? 1 : 0)) |
-		  BITS(VEC_IRQ_ENABLES_MATCH_ROW, 1023));
+#ifdef FIELD_WOBBLE
+		  BITS(VEC_IRQ_ENABLES_MATCH, vec->interlaced) |
+#endif
+		  BITS(VEC_IRQ_ENABLES_MATCH_ROW, 32));
 }
 
 irqreturn_t rp1vec_hw_isr(int irq, void *dev)
@@ -575,6 +629,31 @@ irqreturn_t rp1vec_hw_isr(int irq, void *dev)
 			drm_crtc_handle_vblank(&vec->pipe.crtc);
 		if (u & VEC_IRQ_FLAGS_DONE_BITS)
 			complete(&vec->finished);
+
+#ifdef FIELD_WOBBLE
+		/*
+		 * VEC has native support for interlaced modes, but that only
+		 * supports buffer-flips per frame (30fps), not field (60fps).
+		 * Instead, we always run the VEC front end in a "progressive"
+		 * mode and use the "field-wobble" trick (see RP1 DPI driver).
+		 */
+		if ((u & VEC_IRQ_FLAGS_MATCH_BITS) && vec->interlaced) {
+			unsigned long flags;
+			dma_addr_t a;
+
+			spin_lock_irqsave(&vec->hw_lock, flags);
+			vec->lower_field_flag = !vec->lower_field_flag;
+			a = vec->last_dma_addr;
+			if (a) {
+				if (vec->lower_field_flag)
+					a += vec->last_stride;
+				VEC_WRITE(VEC_DMA_ADDR_H, a >> 32);
+				VEC_WRITE(VEC_DMA_ADDR_L, a & 0xFFFFFFFFu);
+			}
+			spin_unlock_irqrestore(&vec->hw_lock, flags);
+		}
+#endif
 	}
+
 	return u ? IRQ_HANDLED : IRQ_NONE;
 }