@@ -454,8 +454,8 @@ static void hcd_init_fiq(void *cookie)
454454 DWC_ERROR ("Can't claim FIQ" );
455455 BUG ();
456456 }
457- DWC_WARN ("FIQ on core %d" , smp_processor_id ());
458- DWC_WARN ("FIQ ASM at %px length %d" , & _dwc_otg_fiq_stub , (int )(& _dwc_otg_fiq_stub_end - & _dwc_otg_fiq_stub ));
457+ DWC_INFO ("FIQ on core %d" , smp_processor_id ());
458+ DWC_INFO ("FIQ ASM at %px length %d" , & _dwc_otg_fiq_stub , (int )(& _dwc_otg_fiq_stub_end - & _dwc_otg_fiq_stub ));
459459 set_fiq_handler ((void * ) & _dwc_otg_fiq_stub , & _dwc_otg_fiq_stub_end - & _dwc_otg_fiq_stub );
460460 memset (& regs ,0 ,sizeof (regs ));
461461
@@ -482,7 +482,7 @@ static void hcd_init_fiq(void *cookie)
482482 otg_dev -> os_dep .mphi_base + 0x1f0 ;
483483 dwc_otg_hcd -> fiq_state -> mphi_regs .swirq_clr =
484484 otg_dev -> os_dep .mphi_base + 0x1f4 ;
485- DWC_WARN ("Fake MPHI regs_base at %px" ,
485+ DWC_INFO ("Fake MPHI regs_base at %px" ,
486486 dwc_otg_hcd -> fiq_state -> mphi_regs .base );
487487 } else {
488488 dwc_otg_hcd -> fiq_state -> mphi_regs .ctrl =
@@ -493,16 +493,16 @@ static void hcd_init_fiq(void *cookie)
493493 = otg_dev -> os_dep .mphi_base + 0x2c ;
494494 dwc_otg_hcd -> fiq_state -> mphi_regs .intstat
495495 = otg_dev -> os_dep .mphi_base + 0x50 ;
496- DWC_WARN ("MPHI regs_base at %px" ,
496+ DWC_INFO ("MPHI regs_base at %px" ,
497497 dwc_otg_hcd -> fiq_state -> mphi_regs .base );
498498
499499 //Enable mphi peripheral
500500 writel ((1 <<31 ),dwc_otg_hcd -> fiq_state -> mphi_regs .ctrl );
501501#ifdef DEBUG
502502 if (readl (dwc_otg_hcd -> fiq_state -> mphi_regs .ctrl ) & 0x80000000 )
503- DWC_WARN ("MPHI periph has been enabled" );
503+ DWC_INFO ("MPHI periph has been enabled" );
504504 else
505- DWC_WARN ("MPHI periph has NOT been enabled" );
505+ DWC_INFO ("MPHI periph has NOT been enabled" );
506506#endif
507507 }
508508 // Enable FIQ interrupt from USB peripheral
0 commit comments