clk: rp1: Correct declarations of divider parents

PLL dividers are registered using the clk_hw in the clk_divider member
of rp1_clk_desc, rather than the direct clk_hw member. In order for
parent location to work, parent declarations must link to
&<clock>.div.hw, not &<clock>.hw.

Signed-off-by: Phil Elwell <[email protected]>

Author: pelwell

drivers/clk/clk-rp1.c

@@ -1429,7 +1429,7 @@ static struct rp1_clk_desc pll_video_sec_desc = REGISTER_PLL_DIV(
 
 static const struct clk_parent_data clk_eth_tsu_parents[] = {
 	{ .index = 0 },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .index = -1 },
 	{ .index = -1 },
 	{ .index = -1 },
@@ -1460,7 +1460,7 @@ static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK(
 static const struct clk_parent_data clk_eth_parents[] = {
 	{ .hw = &pll_sys_sec_desc.div.hw },
 	{ .hw = &pll_sys_desc.hw },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 };
 
 static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK(
@@ -1661,7 +1661,7 @@ static struct rp1_clk_desc clk_uart_desc = REGISTER_CLK(
 
 static const struct clk_parent_data clk_pwm0_parents[] = {
 	{ .index = -1 },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .index = 0 },
 };
 
@@ -1687,7 +1687,7 @@ static struct rp1_clk_desc clk_pwm0_desc = REGISTER_CLK(
 
 static const struct clk_parent_data clk_pwm1_parents[] = {
 	{ .index = -1 },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .index = 0 },
 };
 
@@ -1715,7 +1715,7 @@ static const struct clk_parent_data clk_audio_in_parents[] = {
 	{ .index = -1 },
 	{ .index = -1 },
 	{ .index = -1 },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .index = 0 },
 };
 
@@ -1740,8 +1740,8 @@ static struct rp1_clk_desc clk_audio_in_desc = REGISTER_CLK(
 
 static const struct clk_parent_data clk_audio_out_parents[] = {
 	{ .index = -1 },
-	{ .hw = &pll_audio_sec_desc.hw },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_audio_sec_desc.div.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .index = 0 },
 };
 
@@ -1767,7 +1767,7 @@ static struct rp1_clk_desc clk_audio_out_desc = REGISTER_CLK(
 static const struct clk_parent_data clk_i2s_parents[] = {
 	{ .index = 0 },
 	{ .hw = &pll_audio_desc.hw },
-	{ .hw = &pll_audio_sec_desc.hw },
+	{ .hw = &pll_audio_sec_desc.div.hw },
 };
 
 static struct rp1_clk_desc clk_i2s_desc = REGISTER_CLK(
@@ -1889,7 +1889,7 @@ static struct rp1_clk_desc clk_sdio_alt_src_desc = REGISTER_CLK(
 
 static const struct clk_parent_data clk_dpi_parents[] = {
 	{ .hw = &pll_sys_desc.hw },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .hw = &pll_video_desc.hw },
 	{ .index = -1 },
 	{ .index = -1 },
@@ -2025,7 +2025,7 @@ static struct rp1_clk_desc clksrc_mipi1_dsi_byteclk_desc = REGISTER_CLK(
 
 static const struct clk_parent_data clk_mipi0_dpi_parents[] = {
 	{ .hw = &pll_sys_desc.hw },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .hw = &pll_video_desc.hw },
 	{ .hw = &clksrc_mipi0_dsi_byteclk_desc.hw },
 	{ .index = -1 },
@@ -2056,7 +2056,7 @@ static struct rp1_clk_desc clk_mipi0_dpi_desc = REGISTER_CLK(
 
 static const struct clk_parent_data clk_mipi1_dpi_parents[] = {
 	{ .hw = &pll_sys_desc.hw },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .hw = &pll_video_desc.hw },
 	{ .hw = &clksrc_mipi1_dsi_byteclk_desc.hw },
 	{ .index = -1 },
@@ -2092,7 +2092,7 @@ static const struct clk_parent_data clk_gp2_parents[] = {
 	{ .index = -1 },
 	{ .index = -1 },
 	{ .index = -1 },
-	{ .hw = &pll_sys_sec_desc.hw },
+	{ .hw = &pll_sys_sec_desc.div.hw },
 	{ .index = -1 },
 	{ .hw = &pll_video_desc.hw },
 	{ .hw = &clk_audio_in_desc.hw },
@@ -2173,7 +2173,7 @@ static const struct clk_parent_data clk_gp4_parents[] = {
 	{ .index = -1 },
 	{ .index = -1 },
 	{ .index = -1 },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .index = -1 },
 	{ .index = -1 },
 	{ .index = -1 },
@@ -2207,7 +2207,7 @@ static struct rp1_clk_desc clk_gp4_desc = REGISTER_CLK(
 
 static const struct clk_parent_data clk_vec_parents[] = {
 	{ .hw = &pll_sys_pri_ph_desc.hw },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .hw = &pll_video_desc.hw },
 	{ .index = -1 },
 	{ .index = -1 },
@@ -2243,7 +2243,7 @@ static const struct clk_parent_data clk_gp5_parents[] = {
 	{ .index = -1 },
 	{ .index = -1 },
 	{ .index = -1 },
-	{ .hw = &pll_video_sec_desc.hw },
+	{ .hw = &pll_video_sec_desc.div.hw },
 	{ .hw = &clk_eth_tsu_desc.hw },
 	{ .index = -1 },
 	{ .hw = &clk_vec_desc.hw },