@@ -69,13 +69,15 @@ struct raspberrypi_clk_variant {
6969 unsigned long min_rate ;
7070 bool minimize ;
7171 bool maximize ;
72+ u32 flags ;
7273};
7374
7475static struct raspberrypi_clk_variant
7576raspberrypi_clk_variants [RPI_FIRMWARE_NUM_CLK_ID ] = {
7677 [RPI_FIRMWARE_ARM_CLK_ID ] = {
7778 .export = true,
7879 .clkdev = "cpu0" ,
80+ .flags = CLK_IS_CRITICAL ,
7981 },
8082 [RPI_FIRMWARE_CORE_CLK_ID ] = {
8183 .export = true,
@@ -91,6 +93,12 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
9193 * always use the minimum the drivers will let us.
9294 */
9395 .minimize = true,
96+
97+ /*
98+ * It should never be disabled as it drives the bus for
99+ * everything else.
100+ */
101+ .flags = CLK_IS_CRITICAL ,
94102 },
95103 [RPI_FIRMWARE_M2MC_CLK_ID ] = {
96104 .export = true,
@@ -116,6 +124,15 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
116124 * drivers will let us.
117125 */
118126 .minimize = true,
127+
128+ /*
129+ * As mentioned above, this clock is disabled during boot,
130+ * the firmware will skip the HSM initialization, resulting
131+ * in a bus lockup. Therefore, make sure it's enabled
132+ * during boot, but after it, it can be enabled/disabled
133+ * by the driver.
134+ */
135+ .flags = CLK_IGNORE_UNUSED ,
119136 },
120137 [RPI_FIRMWARE_V3D_CLK_ID ] = {
121138 .export = true,
@@ -124,10 +141,12 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
124141 [RPI_FIRMWARE_PIXEL_CLK_ID ] = {
125142 .export = true,
126143 .minimize = true,
144+ .flags = CLK_IS_CRITICAL ,
127145 },
128146 [RPI_FIRMWARE_HEVC_CLK_ID ] = {
129147 .export = true,
130148 .minimize = true,
149+ .flags = CLK_IS_CRITICAL ,
131150 },
132151 [RPI_FIRMWARE_ISP_CLK_ID ] = {
133152 .export = true,
@@ -136,6 +155,7 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
136155 [RPI_FIRMWARE_PIXEL_BVB_CLK_ID ] = {
137156 .export = true,
138157 .minimize = true,
158+ .flags = CLK_IS_CRITICAL ,
139159 },
140160 [RPI_FIRMWARE_VEC_CLK_ID ] = {
141161 .export = true,
@@ -266,7 +286,41 @@ static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw,
266286 return 0 ;
267287}
268288
289+ static int raspberrypi_fw_prepare (struct clk_hw * hw )
290+ {
291+ const struct raspberrypi_clk_data * data = clk_hw_to_data (hw );
292+ struct raspberrypi_clk * rpi = data -> rpi ;
293+ u32 state = RPI_FIRMWARE_STATE_ENABLE_BIT ;
294+ int ret ;
295+
296+ ret = raspberrypi_clock_property (rpi -> firmware , data ,
297+ RPI_FIRMWARE_SET_CLOCK_STATE , & state );
298+ if (ret )
299+ dev_err_ratelimited (rpi -> dev ,
300+ "Failed to set clock %s state to on: %d\n" ,
301+ clk_hw_get_name (hw ), ret );
302+
303+ return ret ;
304+ }
305+
306+ static void raspberrypi_fw_unprepare (struct clk_hw * hw )
307+ {
308+ const struct raspberrypi_clk_data * data = clk_hw_to_data (hw );
309+ struct raspberrypi_clk * rpi = data -> rpi ;
310+ u32 state = 0 ;
311+ int ret ;
312+
313+ ret = raspberrypi_clock_property (rpi -> firmware , data ,
314+ RPI_FIRMWARE_SET_CLOCK_STATE , & state );
315+ if (ret )
316+ dev_err_ratelimited (rpi -> dev ,
317+ "Failed to set clock %s state to off: %d\n" ,
318+ clk_hw_get_name (hw ), ret );
319+ }
320+
269321static const struct clk_ops raspberrypi_firmware_clk_ops = {
322+ .prepare = raspberrypi_fw_prepare ,
323+ .unprepare = raspberrypi_fw_unprepare ,
270324 .is_prepared = raspberrypi_fw_is_prepared ,
271325 .recalc_rate = raspberrypi_fw_get_rate ,
272326 .determine_rate = raspberrypi_fw_dumb_determine_rate ,
@@ -296,7 +350,7 @@ static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi,
296350 if (!init .name )
297351 return ERR_PTR (- ENOMEM );
298352 init .ops = & raspberrypi_firmware_clk_ops ;
299- init .flags = CLK_GET_RATE_NOCACHE ;
353+ init .flags = variant -> flags | CLK_GET_RATE_NOCACHE ;
300354
301355 data -> hw .init = & init ;
302356
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