Forward-port downstream pcie-brcmstb patches to 6.14#6675
Forward-port downstream pcie-brcmstb patches to 6.14#6675pelwell merged 45 commits intorpi-6.14.yfrom
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This booted for me, with working ssd/m2hat and ethernet. |
6by9
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6by9
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Seeing as much of this should be destined for upstream, I'm being picky.
And welcome to the lovely world of dt-bindings.
| the time between internal release of fundamental reset and | ||
| the deassertion of the external PERST# pin. This has the | ||
| effect of increasing the Tperst_clk phase of link init. | ||
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Describe the units and range, eg
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 5000
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Strangely, the bindings checker complains if I define this. But not for uint8 (?)
| brcm,fifo-qos-map: | ||
| description: 2712 only. Each nibble assigns all per-TC FIFOs an AXI | ||
| priority based on fullness (backpressure signalling). | ||
| Mutually exclusive with vdm-qos-map. |
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Units and range.
Do we have to encode it within DT, or could it be an array of N values?
Is it mandatory to have one or other of these, or is neither acceptable?
The bit you'll really love is that commenting "2712 only" doesn't wash in bindings. YAML has lots of lovely syntax to denote which compatibles support which properties.
eg https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml#L95-L126
make dt_binding_check checks whether your bindings are valid.
make CHECK_DTBS=y broadcom/bcm2712-rpi-5-b.dts checks whether your dtb file complies with the requirements of the binding.
(Add the relevant environment vars if cross-compiling).
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This is where it gets fun: downstream uses nibbles. Would the upstream preference be a u32 array? Bit wasteful to encode 4 bits in 32.
Also, the useful combinations of these properties are either nothing, or "brcm,fifo-qos-map" or "brcm,vdm-qos-map". Can optional properties be specified as mutually exclusive?
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I would have expected upstream to want an array of u8 or u32, but the only way of finding out would be to ask them.
Wasting <1kB isn't really worth worrying about.
You can convert the DT config directly back into the relevant nibbles for the hardware during probe, so it only throws a small amount extra on the stack during probe.
Yes I believe you can encode mutually exclusion on optional properties. Don't ask me for the exact runes at the moment though.
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I went with an array of u8 - breaks DT compatibility across versions, but them's the breaks.
| description: 2712 only. Each nibble assigns each per-TC FIFO a base AXI | ||
| priority with elevation depending on Vendor Messages from the EP - | ||
| specifically, RP1. | ||
| Mutually exclusive with fifo-qos-map. |
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Minor heads up that there's another pcie-brcmstb patch set just queued up for merging |
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https://lore.kernel.org/linux-arm-kernel/20250214173944.47506-2-james.quinlan@broadcom.com/ obsoletes commit 5ae7f04 but that's a problem for future us. |
Ish. It also means that the your patches should apply upstream for when we try submitting them. (Quickest way to apply the series to the current branch is |
This reverts commit bcdeae7.
This reverts commit 97ad2e0.
This reverts commit a70c281.
This reverts commit 1974bc7.
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…ngs" This reverts commit c4d0832.
Enable pcie1 and pcie2 DT nodes. Pcie1 is used for the extension connector and pcie2 is used for RP1 south-bridge. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
When the user elects to limit the PCIe generation via the appropriate DT property, apply the settings before the PCIe link-up, not after. Fixes: c045213 ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver") Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Fixes: c045213 ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver") Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
The driver was mistakenly writing to a RO config-space register (PCI_EXP_LNKCAP). Although harmless in this case, the proper destination is an internal RW register that is reflected by PCI_EXP_LNKCAP. Fixes: c045213 ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver") Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
When setting a register field it was assumed that the field started at the lsb of the register. Although the masks do indeed start at the lsb, and this will probably not change, it is prudent to use a method that makes no assumption about the mask's placement in the register. The uXXp_replace_bits() calls are used since they are already prevalent in this driver. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
If regulator_bulk_get() returns an error, no regulators are created and we need to set their number to zero. If we do not do this and the PCIe link-up fails, regulator_bulk_free() will be invoked and effect a panic. Also print out the error value, as we cannot return an error upwards as Linux will WARN on an error from add_bus(). Fixes: 9e6be01 ("PCI: brcmstb: Enable child bus device regulators from DT") Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Our system for enabling and disabling regulators is designed to work only on the port driver below the root complex. The conditions to discriminate for this case should be the same when we are adding or removing the bus. Without this change the regulators may be disabled prematurely when a bus further down the tree is removed. Fixes: 9e6be01 ("PCI: brcmstb: Enable child bus device regulators from DT") Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
The constants EXT_CFG_DATA and EXT_CFG_INDEX vary by SOC. One of the map_bus methods used these constants, the other used different constants. Fortunately there was no problem because the SoCs that used the latter map_bus method all had the same register constants. Remove the redundant constants and adjust the code to use them. In addition, update EXT_CFG_DATA to use the 4k-page based config space access system, which is what the second map_bus method was already using. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
The HW team has decided to "tighten" some field definitions in the MDIO packet format. Fortunately these two changes may be made in a backwards compatible manner. The CMD field used to be 12 bits and now is one. This change is backwards compatible because the field's starting bit position is unchanged and the only commands we've used have values 0 and 1. The PORT field's width has been changed from four to five bits. When written, the new bit is not contiguous with the other four. Fortunately, this change is backwards compatible because we have never used anything other than 0 for the port field's value. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Just make it clear to the reader that there is a conversion happening, in this case from an int type to an irq_hw_number_t, an unsigned long int. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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These chips use a UBUS-AXI bridge component that has configurable timeout and error response handling. Suppress AXI error responses to CPU requests, otherwise these are fatal if they reach the ARM cluster, and set reasonably large timeouts for both Mem and Cfg requests. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
In commit b478e16 ("PCI/ASPM: Consolidate link state defines") PCIE_LINK_STATE_L1 and PCIE_LINK_STATE_L0s grew some bits for more granular control of ASPM. This broke the aspm-no-l0s override, instead disabling link ASPM completely if this DT property was specified. Specify the field bits in the driver. Fixes: caab002 ("PCI: brcmstb: Disable L0s component of ASPM if requested") Fixes: 0693b42 ("PCI: brcmstb: Split post-link up initialization to brcm_pcie_start_link()") Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
It appears that bits in the Root Control Register are reset with perst_n, which means the PCI layer's call to enable CRS prior to adding/scanning the bus has no effect. Open-code the enable in brcm_pcie_start_link as a workaround. Without CRS visibility, configuration reads issued by the CPU don't retire if the endpoint returns a CRS response - the RC will poll until a (large) timeout is reached. This means the core can stall for a long time during boot. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
The PHY MDIO register map is different on BCM2712, and as the PHY input clock is 54MHz not 100MHz, enabling refclk SSC is both broken and unfixable. Mask out attempts to enable SSC with a controller quirk. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
There is configurable priority forwarding hardware in this variant of the Root Complex controller. Add optional properties to configure FIFO backpressure or Vendor-Defined Message priority forwarding. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
The BCM2712 root complexes can interpret priority signalling in two different ways, based on the incoming Traffic Class of a TLP. The TLP TCs are assigned to separate internal request/response queues, and assigned different AXI IDs. These queues can have outgoing AXI transactions tagged based on: - Static QoS values - Dynamic QoS through internal backpressure - Dynamic QoS with elevation based on Vendor Messages received by the RC The VDM mechanism is of limited use due to implementation bugs, but the implicit reordering due to separate ID assignment allows higher-priority traffic from an EP to overtake other traffic in the RC and rest of the system. RP1 assigns TCs based on its internal bus managers, and internally tags read requests to allow out-of-order completions, so these two features operate in concert to provide priority service to e.g. MIPI camera or display traffic. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
Some platforms may require an extended time with refclk active before PERST# is released. Add a property to let the RC driver know how long to wait. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
Some endpoints need longer than the minimum Tperst_clk time of 100us that the PCIe specification allows for, as they may need to sequence internal resets off the stable output of internal PLLs prior to removal of fundamental reset. PCIe switches are an especially bad case, in some cases requiring up to 100 milliseconds for stable downstream link behaviour. Parse the DT property brcm,tperst-clk-ms and use this to hold PERST# low during brcm_pcie_start_link(). The BRCM RC typically outputs 200us of stable refclk before deasserting PERST#. By masking/forcing the output signal while deasserting the internal reset, the effect is to extend the length of time that the refclk is active and stable before PERST# is released. The TX lanes will enter the Polling state before PERST# is released, but this appears to be harmless. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
pcie1 should use the FIFO threshold property as the RC should not pay attention to Vendor Messages from incompatible endpoint hardware. Also drop the downstream MPS property, it's no longer needed. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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This now
The bindings pass dt_binding_check (at least, I think so - lots of others fail). |
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This booted for me, with working ssd/m2hat and ethernet. |
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@6by9 Is there any reason I shouldn't hit the Merge button? |
I don't think there's a good reason not to. Picking up the newer versions of the upstream patches is fine, and P33M is the expert on what the downstream patches do. |
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Thanks! |
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This applies on top of the upstream bcm2712-aware pcie-brcmstb driver and restores downstream bugfixes and compatibility features.
The intent is to keep all the conflated 2712/platform-specific adjustments relatively self-contained, hopefully avoiding merge conflicts until they land upstream.