Forward-port downstream pcie-brcmstb patches to 6.12

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
+
+maintainers:
+  - Stanimir Varbanov <[email protected]>
+
+description:
+  This interrupt controller is used to provide interrupt vectors to the
+  generic interrupt controller (GIC) on bcm2712. It will be used as
+  external MSI-X controller for PCIe root complex.
+
+allOf:
+  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
+
+properties:
+  compatible:
+    const: brcm,bcm2712-mip
+
+  reg:
+    items:
+      - description: Base register address
+      - description: PCIe message address
+
+  "#msi-cells":
+    const: 0
+
+  brcm,msi-offset:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Shift the allocated MSI's.
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - msi-controller
+  - msi-ranges
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    axi {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        msi-controller@1000130000 {
+            compatible = "brcm,bcm2712-mip";
+            reg = <0x10 0x00130000 0x00 0xc0>,
+                  <0xff 0xfffff000 0x00 0x1000>;
+            msi-controller;
+            #msi-cells = <0>;
+            msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
+        };
+    };

Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

@@ -14,6 +14,7 @@ properties:
     items:
       - enum:
           - brcm,bcm2711-pcie # The Raspberry Pi 4
+          - brcm,bcm2712-pcie # Raspberry Pi 5
           - brcm,bcm4908-pcie
           - brcm,bcm7211-pcie # Broadcom STB version of RPi4
           - brcm,bcm7216-pcie # Broadcom 7216 Arm
@@ -83,6 +84,14 @@ properties:
     $ref: /schemas/types.yaml#/definitions/string
     enum: [ safe, no-l1ss, default ]
 
+  brcm,fifo-qos-map:
+    description: Array of u8 elements which assigns every per-TC FIFOs
+      an AXI priority based on fullness quartile (backpressure signalling).
+      Mutually exclusive with vdm-qos-map.
+    $ref: /schemas/types.yaml#/definitions/uint8-array
+    minItems: 4
+    maxItems: 4
+
   brcm,scb-sizes:
     description: u64 giving the 64bit PCIe memory
       viewport size of a memory controller.  There may be up to
@@ -96,13 +105,31 @@ properties:
       minItems: 1
       maxItems: 3
 
+  brcm,tperst-clk-ms:
+    description: u32 giving the number of milliseconds to extend
+      the time between internal release of fundamental reset and
+      the deassertion of the external PERST# pin. This has the
+      effect of increasing the Tperst_clk phase of link init.
+
+  brcm,vdm-qos-map:
+    description: Array of u8 elements which assigns each per-TC FIFO
+      a base AXI priority with automatic elevation depending on
+      Vendor Messages from the EP - specifically, RP1.
+      Mutually exclusive with fifo-qos-map.
+    $ref: /schemas/types.yaml#/definitions/uint8-array
+    minItems: 8
+    maxItems: 8
+
   resets:
     minItems: 1
     maxItems: 3
 
   reset-names:
     minItems: 1
-    maxItems: 3
+    items:
+      - enum: [perst, rescal]
+      - const: bridge
+      - const: swinit
 
   brcm,tperst-clk-ms:
     category: optional
@@ -183,6 +210,17 @@ allOf:
         - resets
         - reset-names
 
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              const: brcm,bcm2712-pcie
+    then:
+      properties:
+        brcm,fifo-qos-map: false
+        brcm,vdm-qos-map: false
+
 unevaluatedProperties: false
 
 examples:

arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts

@@ -422,10 +422,6 @@
 // =============================================
 // Board specific stuff here
 
-&pcie0 {
-       brcm,enable-l1ss;
-};
-
 &sdhost {
 	status = "disabled";
 };

arch/arm/boot/dts/overlays/README

@@ -3703,7 +3703,9 @@ Params: <None>
 Name:   pciex1-compat-pi5
 Info:   Compatibility features for pciex1 on Pi 5.
 Load:   dtoverlay=pciex1-compat-pi5,<param>=<val>
-Params: l1ss                    Enable ASPM L1 sub-state support
+Params: l1ss                    Enable RC ASPM L1 sub-state support. Requires
+                                that the CLKREQ# pin is connected to the
+                                endpoint.
         no-l0s                  Disable ASPM L0s
         no-mip                  Revert to the MSI target in the RC, instead of
                                 the MSI-MIP peripheral. Use if a) more than 8

arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts

@@ -12,7 +12,7 @@
 	fragment@0 {
 		target = <&pciex1>;
 		__dormant__ {
-			brcm,enable-l1ss;
+			brcm,clkreq-mode = "default";
 		};
 	};
 

arch/arm64/boot/dts/broadcom/bcm2712-ds.dtsi

@@ -350,190 +350,6 @@
 		brcm,dma-channel-mask = <0x0fc0>;
 	};
 
-	// Single-lane Gen3 PCIe
-	// Outbound window at 0x14_000000-0x17_ffffff
-	pcie0: pcie@100000 {
-		compatible = "brcm,bcm2712-pcie";
-		reg = <0x10 0x00100000  0x0 0x9310>;
-		device_type = "pci";
-		max-link-speed = <2>;
-		#address-cells = <3>;
-		#interrupt-cells = <1>;
-		#size-cells = <2>;
-		/*
-			* Unused interrupts:
-			* 208: AER
-			* 215: NMI
-			* 216: PME
-			*/
-		interrupt-parent = <&gicv2>;
-		interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pcie", "msi";
-		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
-		interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 2 &gicv2 GIC_SPI 210
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 3 &gicv2 GIC_SPI 211
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 4 &gicv2 GIC_SPI 212
-						IRQ_TYPE_LEVEL_HIGH>;
-		resets = <&bcm_reset 5>, <&bcm_reset 42>, <&pcie_rescal>;
-		reset-names = "swinit", "bridge", "rescal";
-		msi-controller;
-		msi-parent = <&pcie0>;
-
-		ranges = <0x02000000 0x00 0x00000000
-				0x17 0x00000000
-				0x0 0xfffffffc>,
-				<0x43000000 0x04 0x00000000
-				0x14 0x00000000
-				0x3 0x00000000>;
-
-		dma-ranges = <0x43000000 0x10 0x00000000
-					0x00 0x00000000
-					0x10 0x00000000>;
-
-		status = "disabled";
-	};
-
-	// Single-lane Gen3 PCIe
-	// Outbound window at 0x18_000000-0x1b_ffffff
-	pcie1: pcie@110000 {
-		compatible = "brcm,bcm2712-pcie";
-		reg = <0x10 0x00110000  0x0 0x9310>;
-		device_type = "pci";
-		max-link-speed = <2>;
-		#address-cells = <3>;
-		#interrupt-cells = <1>;
-		#size-cells = <2>;
-		/*
-			* Unused interrupts:
-			* 218: AER
-			* 225: NMI
-			* 226: PME
-			*/
-		interrupt-parent = <&gicv2>;
-		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pcie", "msi";
-		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
-		interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 2 &gicv2 GIC_SPI 220
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 3 &gicv2 GIC_SPI 221
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 4 &gicv2 GIC_SPI 222
-						IRQ_TYPE_LEVEL_HIGH>;
-		resets = <&bcm_reset 7>, <&bcm_reset 43>, <&pcie_rescal>;
-		reset-names = "swinit", "bridge", "rescal";
-		msi-controller;
-		msi-parent = <&mip1>;
-
-		// 2GB, 32-bit, non-prefetchable at PCIe 00_80000000
-		ranges = <0x02000000 0x00 0x80000000
-				0x1b 0x80000000
-				0x00 0x80000000>,
-		// 14GB, 64-bit, prefetchable at PCIe 04_00000000
-				<0x43000000 0x04 0x00000000
-				0x18 0x00000000
-				0x03 0x80000000>;
-
-		dma-ranges = <0x03000000 0x10 0x00000000
-					0x00 0x00000000
-					0x10 0x00000000>;
-
-		status = "disabled";
-	};
-
-	pcie_rescal: reset-controller@119500 {
-		compatible = "brcm,bcm7216-pcie-sata-rescal";
-		reg = <0x10 0x00119500  0x0 0x10>;
-		#reset-cells = <0>;
-	};
-
-	// Quad-lane Gen3 PCIe
-	// Outbound window at 0x1c_000000-0x1f_ffffff
-	pcie2: pcie@120000 {
-		compatible = "brcm,bcm2712-pcie";
-		reg = <0x10 0x00120000  0x0 0x9310>;
-		device_type = "pci";
-		max-link-speed = <2>;
-		#address-cells = <3>;
-		#interrupt-cells = <1>;
-		#size-cells = <2>;
-		/*
-			* Unused interrupts:
-			* 228: AER
-			* 235: NMI
-			* 236: PME
-			*/
-		interrupt-parent = <&gicv2>;
-		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pcie", "msi";
-		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
-		interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 2 &gicv2 GIC_SPI 230
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 3 &gicv2 GIC_SPI 231
-						IRQ_TYPE_LEVEL_HIGH>,
-				<0 0 0 4 &gicv2 GIC_SPI 232
-						IRQ_TYPE_LEVEL_HIGH>;
-		resets = <&bcm_reset 32>, <&bcm_reset 44>, <&pcie_rescal>;
-		reset-names = "swinit", "bridge", "rescal";
-		msi-controller;
-		msi-parent = <&mip0>;
-
-		// ~4GB, 32-bit, not-prefetchable at PCIe 00_00000000
-		ranges = <0x02000000 0x00 0x00000000
-				0x1f 0x00000000
-				0x0 0xfffffffc>,
-		// 12GB, 64-bit, prefetchable at PCIe 04_00000000
-				<0x43000000 0x04 0x00000000
-				0x1c 0x00000000
-				0x03 0x00000000>;
-
-		// 64GB system RAM space at PCIe 10_00000000
-		dma-ranges = <0x02000000 0x00 0x00000000
-					0x1f 0x00000000
-					0x00 0x00400000>,
-					<0x43000000 0x10 0x00000000
-					0x00 0x00000000
-					0x10 0x00000000>;
-
-		status = "disabled";
-	};
-
-	mip0: msi-controller@130000 {
-		compatible = "brcm,bcm2712-mip-intc";
-		reg = <0x10 0x00130000  0x0 0xc0>;
-		msi-controller;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		brcm,msi-base-spi = <128>;
-		brcm,msi-num-spis = <64>;
-		brcm,msi-offset = <0>;
-		brcm,msi-pci-addr = <0xff 0xfffff000>;
-	};
-
-	mip1: msi-controller@131000 {
-		compatible = "brcm,bcm2712-mip-intc";
-		reg = <0x10 0x00131000  0x0 0xc0>;
-		msi-controller;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		brcm,msi-base-spi = <247>;
-		/* Actually 20 total, but the others are
-			* both sparse and non-consecutive */
-		brcm,msi-num-spis = <8>;
-		brcm,msi-offset = <8>;
-		brcm,msi-pci-addr = <0xff 0xffffe000>;
-	};
-
 	syscon_piarbctl: syscon@400018 {
 		compatible = "brcm,syscon-piarbctl", "syscon", "simple-mfd";
 		reg = <0x10 0x00400018  0x0 0x18>;
@@ -590,12 +406,6 @@
 		status = "disabled";
 	};
 
-	bcm_reset: reset-controller@1504318 {
-		compatible = "brcm,brcmstb-reset";
-		reg = <0x10 0x01504318  0x0 0x30>;
-		#reset-cells = <1>;
-	};
-
 	v3d: v3d@2000000 {
 		compatible = "brcm,2712-v3d";
 		reg = <0x10 0x02000000  0x0 0x4000>,
@@ -674,3 +484,12 @@
 &vc4 {
 	status = "disabled";
 };
+
+&pcie1 {
+	brcm,fifo-qos-map = /bits/ 8 <3 3 3 3>;
+	status = "disabled";
+};
+
+&pcie2 {
+	brcm,vdm-qos-map = /bits/ 8 <8 8 8 9 10 10 11 11>;
+};