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kilograhamkilograham
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Merge branch 'master' into develop
2 parents 0d4a9f2 + 465a2a3 commit cbf8072

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3 files changed

+91
-113
lines changed

3 files changed

+91
-113
lines changed

‎pico_w/wifi/ntp_client/picow_ntp_client.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ static void ntp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_ad
108108

109109
// Perform initialisation
110110
static NTP_T* ntp_init(void) {
111-
NTP_T *state = calloc(1, sizeof(NTP_T));
111+
NTP_T *state = (NTP_T*)calloc(1, sizeof(NTP_T));
112112
if (!state) {
113113
printf("failed to allocate state\n");
114114
return NULL;
@@ -183,4 +183,4 @@ int main() {
183183
run_ntp_test();
184184
cyw43_arch_deinit();
185185
return 0;
186-
}
186+
}

‎pio/quadrature_encoder/quadrature_encoder.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/**
2-
* Copyright (c) 2021 pmarques-dev @ github
2+
* Copyright (c) 2023 Raspberry Pi (Trading) Ltd.
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -44,8 +44,10 @@ int main() {
4444
PIO pio = pio0;
4545
const uint sm = 0;
4646

47-
uint offset = pio_add_program(pio, &quadrature_encoder_program);
48-
quadrature_encoder_program_init(pio, sm, offset, PIN_AB, 0);
47+
// we don't really need to keep the offset, as this program must be loaded
48+
// at offset 0
49+
pio_add_program(pio, &quadrature_encoder_program);
50+
quadrature_encoder_program_init(pio, sm, PIN_AB, 0);
4951

5052
while (1) {
5153
// note: thanks to two's complement arithmetic delta will always

‎pio/quadrature_encoder/quadrature_encoder.pio

Lines changed: 84 additions & 108 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
11
;
2-
; Copyright (c) 2021 pmarques-dev @ github
2+
; Copyright (c) 2023 Raspberry Pi (Trading) Ltd.
33
;
44
; SPDX-License-Identifier: BSD-3-Clause
55
;
66

77
.program quadrature_encoder
88

9-
; this code must be loaded into address 0, but at 29 instructions, it probably
10-
; wouldn't be able to share space with other programs anyway
9+
; the code must be loaded at address 0, because it uses computed jumps
1110
.origin 0
1211

1312

@@ -20,82 +19,70 @@
2019
; keeps the current encoder count and is incremented / decremented according to
2120
; the steps sampled
2221

23-
; writing any non zero value to the TX FIFO makes the state machine push the
24-
; current count to RX FIFO between 6 to 18 clocks afterwards. The worst case
25-
; sampling loop takes 14 cycles, so this program is able to read step rates up
26-
; to sysclk / 14 (e.g., sysclk 125MHz, max step rate = 8.9 Msteps/sec)
27-
22+
; the program keeps trying to write the current count to the RX FIFO without
23+
; blocking. To read the current count, the user code must drain the FIFO first
24+
; and wait for a fresh sample (takes ~4 SM cycles on average). The worst case
25+
; sampling loop takes 10 cycles, so this program is able to read step rates up
26+
; to sysclk / 10 (e.g., sysclk 125MHz, max step rate = 12.5 Msteps/sec)
2827

2928
; 00 state
30-
JMP update ; read 00
31-
JMP decrement ; read 01
32-
JMP increment ; read 10
33-
JMP update ; read 11
29+
JMP update ; read 00
30+
JMP decrement ; read 01
31+
JMP increment ; read 10
32+
JMP update ; read 11
3433

3534
; 01 state
36-
JMP increment ; read 00
37-
JMP update ; read 01
38-
JMP update ; read 10
39-
JMP decrement ; read 11
35+
JMP increment ; read 00
36+
JMP update ; read 01
37+
JMP update ; read 10
38+
JMP decrement ; read 11
4039

4140
; 10 state
42-
JMP decrement ; read 00
43-
JMP update ; read 01
44-
JMP update ; read 10
45-
JMP increment ; read 11
41+
JMP decrement ; read 00
42+
JMP update ; read 01
43+
JMP update ; read 10
44+
JMP increment ; read 11
4645

4746
; to reduce code size, the last 2 states are implemented in place and become the
4847
; target for the other jumps
4948

5049
; 11 state
51-
JMP update ; read 00
52-
JMP increment ; read 01
50+
JMP update ; read 00
51+
JMP increment ; read 01
5352
decrement:
54-
; note: the target of this instruction must be the next address, so that
55-
; the effect of the instruction does not depend on the value of Y. The
56-
; same is true for the "JMP X--" below. Basically "JMP Y--, <next addr>"
57-
; is just a pure "decrement Y" instruction, with no other side effects
58-
JMP Y--, update ; read 10
53+
; note: the target of this instruction must be the next address, so that
54+
; the effect of the instruction does not depend on the value of Y. The
55+
; same is true for the "JMP X--" below. Basically "JMP Y--, <next addr>"
56+
; is just a pure "decrement Y" instruction, with no other side effects
57+
JMP Y--, update ; read 10
5958

60-
; this is where the main loop starts
59+
; this is where the main loop starts
6160
.wrap_target
6261
update:
63-
; we start by checking the TX FIFO to see if the main code is asking for
64-
; the current count after the PULL noblock, OSR will have either 0 if
65-
; there was nothing or the value that was there
66-
SET X, 0
67-
PULL noblock
68-
69-
; since there are not many free registers, and PULL is done into OSR, we
70-
; have to do some juggling to avoid losing the state information and
71-
; still place the values where we need them
72-
MOV X, OSR
73-
MOV OSR, ISR
74-
75-
; the main code did not ask for the count, so just go to "sample_pins"
76-
JMP !X, sample_pins
77-
78-
; if it did ask for the count, then we push it
79-
MOV ISR, Y ; we trash ISR, but we already have a copy in OSR
80-
PUSH
62+
MOV ISR, Y ; read 11
63+
PUSH noblock
8164

8265
sample_pins:
83-
; we shift into ISR the last state of the 2 input pins (now in OSR) and
84-
; the new state of the 2 pins, thus producing the 4 bit target for the
85-
; computed jump into the correct action for this state
86-
MOV ISR, NULL
87-
IN OSR, 2
88-
IN PINS, 2
89-
MOV PC, ISR
90-
91-
; the PIO does not have a increment instruction, so to do that we do a
92-
; negate, decrement, negate sequence
66+
; we shift into ISR the last state of the 2 input pins (now in OSR) and
67+
; the new state of the 2 pins, thus producing the 4 bit target for the
68+
; computed jump into the correct action for this state. Both the PUSH
69+
; above and the OUT below zero out the other bits in ISR
70+
OUT ISR, 2
71+
IN PINS, 2
72+
73+
; save the state in the OSR, so that we can use ISR for other purposes
74+
MOV OSR, ISR
75+
; jump to the correct state machine action
76+
MOV PC, ISR
77+
78+
; the PIO does not have a increment instruction, so to do that we do a
79+
; negate, decrement, negate sequence
9380
increment:
94-
MOV X, !Y
95-
JMP X--, increment_cont
81+
MOV Y, ~Y
82+
JMP Y--, increment_cont
9683
increment_cont:
97-
MOV Y, !X
98-
.wrap ; the .wrap here avoids one jump instruction and saves a cycle too
84+
MOV Y, ~Y
85+
.wrap ; the .wrap here avoids one jump instruction and saves a cycle too
9986

10087

10188

@@ -106,60 +93,49 @@ increment_cont:
10693

10794
// max_step_rate is used to lower the clock of the state machine to save power
10895
// if the application doesn't require a very high sampling rate. Passing zero
109-
// will set the clock to the maximum, which gives a max step rate of around
110-
// 8.9 Msteps/sec at 125MHz
96+
// will set the clock to the maximum
11197

112-
static inline void quadrature_encoder_program_init(PIO pio, uint sm, uint offset, uint pin, int max_step_rate)
98+
static inline void quadrature_encoder_program_init(PIO pio, uint sm, uint pin, int max_step_rate)
11399
{
114-
pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false);
115-
gpio_pull_up(pin);
116-
gpio_pull_up(pin + 1);
117-
118-
pio_sm_config c = quadrature_encoder_program_get_default_config(offset);
119-
sm_config_set_in_pins(&c, pin); // for WAIT, IN
120-
sm_config_set_jmp_pin(&c, pin); // for JMP
121-
// shift to left, autopull disabled
122-
sm_config_set_in_shift(&c, false, false, 32);
123-
// don't join FIFO's
124-
sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE);
125-
126-
// passing "0" as the sample frequency,
127-
if (max_step_rate == 0) {
128-
sm_config_set_clkdiv(&c, 1.0);
129-
} else {
130-
// one state machine loop takes at most 14 cycles
131-
float div = (float)clock_get_hz(clk_sys) / (14 * max_step_rate);
132-
sm_config_set_clkdiv(&c, div);
133-
}
134-
135-
pio_sm_init(pio, sm, offset, &c);
136-
pio_sm_set_enabled(pio, sm, true);
137-
}
138-
139-
140-
// When requesting the current count we may have to wait a few cycles (average
141-
// ~11 sysclk cycles) for the state machine to reply. If we are reading multiple
142-
// encoders, we may request them all in one go and then fetch them all, thus
143-
// avoiding doing the wait multiple times. If we are reading just one encoder,
144-
// we can use the "get_count" function to request and wait
145-
146-
static inline void quadrature_encoder_request_count(PIO pio, uint sm)
147-
{
148-
pio->txf[sm] = 1;
149-
}
150-
151-
static inline int32_t quadrature_encoder_fetch_count(PIO pio, uint sm)
152-
{
153-
while (pio_sm_is_rx_fifo_empty(pio, sm))
154-
tight_loop_contents();
155-
return pio->rxf[sm];
100+
pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false);
101+
gpio_pull_up(pin);
102+
gpio_pull_up(pin + 1);
103+
104+
pio_sm_config c = quadrature_encoder_program_get_default_config(0);
105+
106+
sm_config_set_in_pins(&c, pin); // for WAIT, IN
107+
sm_config_set_jmp_pin(&c, pin); // for JMP
108+
// shift to left, autopull disabled
109+
sm_config_set_in_shift(&c, false, false, 32);
110+
// don't join FIFO's
111+
sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE);
112+
113+
// passing "0" as the sample frequency,
114+
if (max_step_rate == 0) {
115+
sm_config_set_clkdiv(&c, 1.0);
116+
} else {
117+
// one state machine loop takes at most 10 cycles
118+
float div = (float)clock_get_hz(clk_sys) / (10 * max_step_rate);
119+
sm_config_set_clkdiv(&c, div);
120+
}
121+
122+
pio_sm_init(pio, sm, 0, &c);
123+
pio_sm_set_enabled(pio, sm, true);
156124
}
157125

158126
static inline int32_t quadrature_encoder_get_count(PIO pio, uint sm)
159127
{
160-
quadrature_encoder_request_count(pio, sm);
161-
return quadrature_encoder_fetch_count(pio, sm);
128+
uint ret;
129+
int n;
130+
131+
// if the FIFO has N entries, we fetch them to drain the FIFO,
132+
// plus one entry which will be guaranteed to not be stale
133+
n = pio_sm_get_rx_fifo_level(pio, sm) + 1;
134+
while (n > 0) {
135+
ret = pio_sm_get_blocking(pio, sm);
136+
n--;
137+
}
138+
return ret;
162139
}
163140

164141
%}
165-

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