fix delay after vreg setting to use XOSC clocked CPU

Author: kilograham

src/rp2_common/hardware_clocks/include/hardware/clocks.h

@@ -231,7 +231,7 @@ extern "C" {
 #endif
 #endif // PICO_RP2040 && SYS_CLK_KHZ == 200000 && XOSC_KHZ == 12000 && PLL_COMMON_REFDIV == 1
 
-// PICO_CONFIG: SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US, Number of microseconds to wait after updating regular voltage due to SYS_CLK_VREG_VOLTAGE_MIN to allow voltage to settle, type=bool, default=1, advanced=true, group=hardware_clocks
+// PICO_CONFIG: SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US, Number of microseconds to wait after updating regulator voltage due to SYS_CLK_VREG_VOLTAGE_MIN to allow voltage to settle, type=bool, default=1, advanced=true, group=hardware_clocks
 #ifndef SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US
 #define SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US 1000
 #endif

src/rp2_common/pico_runtime_init/runtime_init_clocks.c

@@ -69,13 +69,6 @@ void __weak runtime_init_clocks(void) {
         pll_init(pll_usb, PLL_USB_REFDIV, PLL_USB_VCO_FREQ_HZ, PLL_USB_POSTDIV1, PLL_USB_POSTDIV2);
         /// \end::pll_init[]
 
-#if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN)
-        if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) {
-            vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN);
-            // wait for voltage to settle
-            busy_wait_us_32(SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US);
-        }
-#endif
         // Configure clocks
 
         // RP2040 CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz
@@ -94,6 +87,15 @@ void __weak runtime_init_clocks(void) {
                         0,
                         XOSC_HZ);
 
+        // This must be done after we've configured CLK_REF to XOSC due to the need to time a delay
+#if SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST && defined(SYS_CLK_VREG_VOLTAGE_MIN)
+        if (vreg_get_voltage() < SYS_CLK_VREG_VOLTAGE_MIN) {
+            vreg_set_voltage(SYS_CLK_VREG_VOLTAGE_MIN);
+            // wait for voltage to settle; must use CPU cycles as TIMER is not yet clocked correctly
+            busy_wait_at_least_cycles((uint32_t)((SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US * (uint64_t)XOSC_HZ) / 1000000));
+        }
+#endif
+
         /// \tag::configure_clk_sys[]
         // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz
         clock_configure_undivided(clk_sys,