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Merged
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Jul 28, 2025
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fix errors/missing info in generated headers/SVD #2599

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28 changes: 17 additions & 11 deletions src/rp2350/hardware_regs/RP2350.svd
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Expand Up @@ -1759,7 +1759,7 @@ SPDX-License-Identifier: BSD-3-Clause
<name>CLK_SYS_CTRL</name>
<addressOffset>0x0000003c</addressOffset>
<description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
<resetValue>0x00000000</resetValue>
<resetValue>0x00000041</resetValue>
<fields>
<field>
<name>AUXSRC</name>
Expand Down Expand Up @@ -43232,7 +43232,8 @@ SPDX-License-Identifier: BSD-3-Clause
<fields>
<field>
<name>AUXCTRL</name>
<description>* Bits 7:2: Reserved
<description>* Bits 7:3: Reserved
* Bit 2: Set to mask OTP power analogue power supply detection from resetting OTP controller and PSM

* Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled.

Expand Down Expand Up @@ -47936,9 +47937,9 @@ SPDX-License-Identifier: BSD-3-Clause
<name>FREQ_RANGE</name>
<description>Controls the number of delay stages in the ROSC ring
LOW uses stages 0 to 7
MEDIUM uses stages 2 to 7
HIGH uses stages 4 to 7
TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications
MEDIUM uses stages 0 to 5
HIGH uses stages 0 to 3
TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications
The clock output will not glitch when changing the range up one step at a time
The clock output will glitch when changing the range down
Note: the values here are gray coded which is why HIGH comes before TOOHIGH</description>
Expand Down Expand Up @@ -47976,7 +47977,7 @@ SPDX-License-Identifier: BSD-3-Clause
2 bits set triples drive strength
3 bits set quadruples drive strength
For frequency randomisation set both DS0_RANDOM=1 &amp; DS1_RANDOM=1</description>
<resetValue>0x00000000</resetValue>
<resetValue>0x00000088</resetValue>
<fields>
<field>
<name>PASSWD</name>
Expand Down Expand Up @@ -49053,51 +49054,56 @@ SPDX-License-Identifier: BSD-3-Clause
bit 0 = SRAM1
0 = powered up
1 = powered down
When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.</description>
When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore being powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.</description>
<resetValue>0x0000000f</resetValue>
<fields>
<field>
<name>CHANGING</name>
<description>Indicates a power state change is in progress</description>
<bitRange>[13:13]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WAITING</name>
<description>Indicates the power manager has received a state change request and is waiting for other actions to complete before executing it</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BAD_HW_REQ</name>
<description>Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)</description>
<description>Invalid hardware initiated state request, power up requests actioned, power down requests ignored</description>
<bitRange>[11:11]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BAD_SW_REQ</name>
<description>Bad software initiated state request. No action taken.</description>
<description>Invalid software initiated state request ignored</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PWRUP_WHILE_WAITING</name>
<description>Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down.</description>
<description>Indicates that a power state change request was ignored because of a pending power state change request</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>REQ_IGNORED</name>
<description>Indicates that a software state change request was ignored because it clashed with an ongoing hardware or debugger request</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>REQ</name>
<description>This is written by software or hardware to request a new power state</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CURRENT</name>
<description>Indicates the current power state</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
Expand Down Expand Up @@ -77606,7 +77612,7 @@ SPDX-License-Identifier: BSD-3-Clause
</field>
<field>
<name>SUSPENDED</name>
<description>Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
<description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
Expand Down
6 changes: 3 additions & 3 deletions src/rp2350/hardware_regs/include/hardware/regs/clocks.h
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Expand Up @@ -615,7 +615,7 @@
// Description : Clock control, can be changed on-the-fly (except for auxsrc)
#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c)
#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1)
#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000)
#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000041)
// -----------------------------------------------------------------------------
// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC
// Description : Selects the auxiliary clock source, will glitch when switching
Expand All @@ -625,7 +625,7 @@
// 0x3 -> xosc_clksrc
// 0x4 -> clksrc_gpin0
// 0x5 -> clksrc_gpin1
#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0)
#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x2)
#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0)
#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7)
#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5)
Expand All @@ -642,7 +642,7 @@
// fly
// 0x0 -> clk_ref
// 0x1 -> clksrc_clk_sys_aux
#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0)
#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x1)
#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001)
#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0)
#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0)
Expand Down
8 changes: 4 additions & 4 deletions src/rp2350/hardware_regs/include/hardware/regs/dreq.h
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Expand Up @@ -121,8 +121,8 @@ typedef enum dreq_num_rp2350 {
DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ
DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ
DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ
DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ
DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ
DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 10's Wrap Value as DREQ
DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 11's Wrap Value as DREQ
DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ
DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ
DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ
Expand All @@ -135,8 +135,8 @@ typedef enum dreq_num_rp2350 {
DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ
DREQ_SHA256 = 54, ///< Select SHA256 as DREQ
DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER1 as DREQ
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER2 as DREQ
DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
DREQ_FORCE = 63, ///< Select FORCE as DREQ
DREQ_COUNT
Expand Down
6 changes: 2 additions & 4 deletions src/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h
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Expand Up @@ -37,8 +37,7 @@
#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000)
// =============================================================================
// Register : GLITCH_DETECTOR_DISARM
// Description : None
// Forcibly disarm the glitch detectors, if they are armed by OTP.
// Description : Forcibly disarm the glitch detectors, if they are armed by OTP.
// Ignored if ARM is YES.
//
// This register is Secure read/write only.
Expand Down Expand Up @@ -142,8 +141,7 @@
#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW"
// =============================================================================
// Register : GLITCH_DETECTOR_LOCK
// Description : None
// Write any nonzero value to disable writes to ARM, DISARM,
// Description : Write any nonzero value to disable writes to ARM, DISARM,
// SENSITIVITY and LOCK. This register is Secure read/write only.
#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c)
#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff)
Expand Down
24 changes: 12 additions & 12 deletions src/rp2350/hardware_regs/include/hardware/regs/intctrl.h
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Expand Up @@ -79,8 +79,8 @@ typedef enum irq_num_rp2350 {
TIMER1_IRQ_1 = 5, ///< Select TIMER1's IRQ 1 output
TIMER1_IRQ_2 = 6, ///< Select TIMER1's IRQ 2 output
TIMER1_IRQ_3 = 7, ///< Select TIMER1's IRQ 3 output
PWM_IRQ_WRAP_0 = 8, ///< Select PWM's IRQ_WRAP 0 output
PWM_IRQ_WRAP_1 = 9, ///< Select PWM's IRQ_WRAP 1 output
PWM_IRQ_WRAP_0 = 8, ///< Select PWM's WRAP_0 IRQ output
PWM_IRQ_WRAP_1 = 9, ///< Select PWM's WRAP_1 IRQ output
DMA_IRQ_0 = 10, ///< Select DMA's IRQ 0 output
DMA_IRQ_1 = 11, ///< Select DMA's IRQ 1 output
DMA_IRQ_2 = 12, ///< Select DMA's IRQ 2 output
Expand All @@ -96,27 +96,27 @@ typedef enum irq_num_rp2350 {
IO_IRQ_BANK0_NS = 22, ///< Select IO_BANK0_NS's IRQ output
IO_IRQ_QSPI = 23, ///< Select IO_QSPI's IRQ output
IO_IRQ_QSPI_NS = 24, ///< Select IO_QSPI_NS's IRQ output
SIO_IRQ_FIFO = 25, ///< Select SIO's IRQ_FIFO output
SIO_IRQ_BELL = 26, ///< Select SIO's IRQ_BELL output
SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's IRQ_FIFO output
SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's IRQ_BELL output
SIO_IRQ_MTIMECMP = 29, ///< Select SIO_IRQ_MTIMECMP's IRQ output
SIO_IRQ_FIFO = 25, ///< Select SIO's FIFO IRQ output
SIO_IRQ_BELL = 26, ///< Select SIO's BELL IRQ output
SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's FIFO IRQ output
SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's BELL IRQ output
SIO_IRQ_MTIMECMP = 29, ///< Select SIO's MTIMECMP IRQ output
CLOCKS_IRQ = 30, ///< Select CLOCKS's IRQ output
SPI0_IRQ = 31, ///< Select SPI0's IRQ output
SPI1_IRQ = 32, ///< Select SPI1's IRQ output
UART0_IRQ = 33, ///< Select UART0's IRQ output
UART1_IRQ = 34, ///< Select UART1's IRQ output
ADC_IRQ_FIFO = 35, ///< Select ADC's IRQ_FIFO output
ADC_IRQ_FIFO = 35, ///< Select ADC's FIFO IRQ output
I2C0_IRQ = 36, ///< Select I2C0's IRQ output
I2C1_IRQ = 37, ///< Select I2C1's IRQ output
OTP_IRQ = 38, ///< Select OTP's IRQ output
TRNG_IRQ = 39, ///< Select TRNG's IRQ output
PROC0_IRQ_CTI = 40, ///< Select PROC0's IRQ_CTI output
PROC1_IRQ_CTI = 41, ///< Select PROC1's IRQ_CTI output
PROC0_IRQ_CTI = 40, ///< Select PROC0's CTI IRQ output
PROC1_IRQ_CTI = 41, ///< Select PROC1's CTI IRQ output
PLL_SYS_IRQ = 42, ///< Select PLL_SYS's IRQ output
PLL_USB_IRQ = 43, ///< Select PLL_USB's IRQ output
POWMAN_IRQ_POW = 44, ///< Select POWMAN's IRQ_POW output
POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's IRQ_TIMER output
POWMAN_IRQ_POW = 44, ///< Select POWMAN's POW IRQ output
POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's TIMER IRQ output
SPARE_IRQ_0 = 46, ///< Select SPARE IRQ 0
SPARE_IRQ_1 = 47, ///< Select SPARE IRQ 1
SPARE_IRQ_2 = 48, ///< Select SPARE IRQ 2
Expand Down
6 changes: 2 additions & 4 deletions src/rp2350/hardware_regs/include/hardware/regs/pio.h
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Expand Up @@ -461,8 +461,7 @@
// =============================================================================
// Register : PIO_DBG_PADOUT
// Description : Read to sample the pad output values PIO is currently driving
// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most
// significant bits are hardwired to 0.
// to the GPIOs.
#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
#define PIO_DBG_PADOUT_BITS _u(0xffffffff)
#define PIO_DBG_PADOUT_RESET _u(0x00000000)
Expand All @@ -472,8 +471,7 @@
// =============================================================================
// Register : PIO_DBG_PADOE
// Description : Read to sample the pad output enables (direction) PIO is
// currently driving to the GPIOs. On RP2040 there are 30 GPIOs,
// so the two most significant bits are hardwired to 0.
// currently driving to the GPIOs.
#define PIO_DBG_PADOE_OFFSET _u(0x00000040)
#define PIO_DBG_PADOE_BITS _u(0xffffffff)
#define PIO_DBG_PADOE_RESET _u(0x00000000)
Expand Down
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