Merge remote-tracking branch 'upstream/staging'

Author: jiegec

.travis.yml

@@ -3,26 +3,21 @@ language: rust
 env:
   - TARGET=x86_64-unknown-linux-gnu
   - TARGET=riscv32imac-unknown-none-elf
+  - TARGET=riscv64imac-unknown-none-elf
+  - TARGET=riscv64gc-unknown-none-elf
 
 rust:
   - nightly
   - stable
-  - 1.31.0 # MSRV
+  - 1.42.0 # MSRV
 
 if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
 matrix:
   allow_failures:
     - rust: nightly
-  include:
-    - env: TARGET=riscv64imac-unknown-none-elf
-      rust: nightly
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    - env: TARGET=riscv64gc-unknown-none-elf
-      rust: nightly
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
+  include:
     - env: CHECK_BLOBS=1
       rust:
       language: bash

CHANGELOG.md

@@ -7,11 +7,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.6.0] - 2020-06-20
+
 ### Changed
 
-- Updated Minimum Supported Rust Version to 1.31.0
+- `Mtvec::trap_mode()`, `Stvec::trap_mode()` and `Utvec::trap_mode()` functions now return `Option<TrapMode>` (breaking change)
+- Updated Minimum Supported Rust Version to 1.42.0
 - Use `llvm_asm!` instead of `asm!`
 
+### Removed
+
+- vexriscv-specific registers were moved to the `vexriscv` crate
+
 ## [v0.5.6] - 2020-03-14
 
 ### Added
@@ -32,6 +39,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Fixed MSRV by restricting the upper bound of `bare-metal` version
 
-[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.5.6...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.6.0...HEAD
+[v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
 [v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6
 [v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv"
-version = "0.5.6"
+version = "0.6.0"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "hardware-support", "no-std"]

README.md

@@ -12,12 +12,12 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.31.0 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.42.0 and up. It *might*
 compile with older versions but that may change in any new patch release.
 
 ## License
 
-Copyright 2019 [RISC-V team][team]
+Copyright 2019-2020 [RISC-V team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice

asm.S

@@ -273,10 +273,3 @@ RW(0x7A3, tdata3)   // Third Debug/Trace trigger data register
 RW(0x7B0, dcsr)     // Debug control and status register
 RW(0x7B1, dpc)      // Debug PC
 RW(0x7B2, dscratch) // Debug scratch register
-
-// VexRiscv custom registers
-RW(0xBC0, vmim)     // Machine IRQ Mask
-RO(0xFC0, vmip)     // Machine IRQ Pending
-RW(0x9C0, vsim)     // Supervisor IRQ Mask
-RO(0xDC0, vsip)     // Supervisor IRQ Pending
-RO(0xCC0, vdci)     // DCache Info

bin/riscv32i-unknown-none-elf.a

@@ -2,10 +2,8 @@
 //!
 //! # Minimum Supported Rust Version (MSRV)
 //!
-//! This crate is guaranteed to compile on stable Rust 1.31 and up. It *might*
+//! This crate is guaranteed to compile on stable Rust 1.42 and up. It *might*
 //! compile with older versions but that may change in any new patch release.
-//! Note that `riscv64imac-unknown-none-elf` and `riscv64gc-unknown-none-elf` targets
-//! are not supported on stable yet.
 //!
 //! # Features
 //!